CODEWITHSUNDEEP
vhdl
wattbatt
wattbatt

Reputation: 477

Is there a way in VHDL to make a series of components?

Simply put, I have a component " X " and I want to connect 24 of them in a row; obviously means that the output of one is the input of the next one; I could just write them myself with copypaste and link them but I wonder if there is a way to do this elegantly.

I know the instruction for I in N downto 0 generate but I don't think I can use it to create components in series, it only creates components in parallel, where each one works on a different value of the I parameter, or not ?

Upvotes: 0

Views: 1543

Answers (1)

Renaud Pacalet
Renaud Pacalet

Reputation: 28945

The generate statement is indeed what you need. Example if your X component has one input a and one output b of type bit:

entity bar is
end entity bar;

architecture rtl of bar is
  signal c: bit_vector(0 to 24);
  component x is
    port(
      a: in  bit;
      b: out bit
    );
  end component x;
begin
  u0: for i in 0 to 23 generate
    x0: x
    port map(
      a => c(i),
      b => c(i+1)
    );
  end generate u0;
end architecture rtl;

The input of the first X instance is c(0) and the output of the last one is c(24).

Upvotes: 1

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