CODEWITHSUNDEEP
vhdl
spiderplant0
spiderplant0

Reputation: 3952

Assignment to part of a multi-dimentional array in VHDL

I want to change some of the elements in an array, but can figure out how to do it.

This line: sig3(1) <= (11, 12); gives me an error

entity t1 is
end entity;

architecture testbench of t1 is

    type type3 is array(1 to 2, 1 to 2) of integer;

    signal sig3 : type3;

begin
    process is
    begin
        -- sig3 <= ((11, 12), (13, 14));  -- this works
        sig3(1) <= (11, 12);   -- get error:  "Incompatible types for assignment."
        wait;
    end process;
end architecture;

Upvotes: 1

Views: 261

Answers (1)

OllieB
OllieB

Reputation: 1431

The way you have defined the array unfortunately precludes the method you favour of assigning: If you decalre a type like this:

type type3 is array(1 to 2, 1 to 2) of integer;
signal sig3 : type3;

Assignments have to fully specify the index:

sig3(1,1) <= 11;
sig3(1,2) <= 12;

You can define a 2d array as a array of 1-d arrays though

type type4 is array(1 to 2) of integer;
type type5 is array(1 to 2) of type4;
signal sig5 : type5;

You can now assign it like this:

sig5(1) <= (11,12);

Unfortunately, you can't work so easily in the other dimension.

Upvotes: 3

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