CODEWITHSUNDEEP
arrays2dvhdlassignment-operator
Sre M
Sre M

Reputation: 1

2D Array assign problem VHDL having different size

I have two 2D arrays defined as below

type ram_1300_block is array (1300 downto 0) of std_logic_vector(7 downto 0);

type ram_2700_block is array (2700 downto 0) of std_logic_vector(7 downto 0);

rx_ram : ram_1300_block;
Q1_ram : ram_2700_block;

Then I am using the below assignment statement in my code:

Q1_ram(1300 downto 1) <= rx_ram(1341 downto 42);

While synthesizing I am getting the below error in vivado 2015.3

Synth 8-2234 indexed name is not a ram_3700 block?

Any workaround?

I dont want to increase the small array size due to resource constraint.

Upvotes: 0

Views: 475

Answers (1)

Tricky
Tricky

Reputation: 4461

This is because VHDL is a stronly typed language. Here rx_ram and Q1_ram are different types, and hence cannot be directly assigned to one another. Even more difficult, because you have assigned a size to your types, you cannot do a type conversion because the slices have no distinct type that can be named for a closely related type conversion.

I recommend you create a type that is unconstrained, that is constrained when you create the signals, and hence can be assigned to one another. You can even create named subtypes if you wish:

type ram_block_t is array(natural range <>) of std_logic_vector(7 downto 0);
subtype ram_1300_block is ram_block_t(1300 downto 0);
subtype ram_2700_block is ram_block_t(2700 downto 0);

signal rx_ram : ram_2700_block ;
signal Q1_ram : ram_1300_block;

Q1_ram(1300 downto 1) <= rx_ram(1341 downto 42);

Note1: I assumed you had the types wrong in your original post, as rx_ram(1341 downto 42) uses index that are out of range for the type.

Note2: The names of the signals and types are likely bad, as I do not know any tool that will infer RAM with such large assignments.

Upvotes: 1

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