CODEWITHSUNDEEP
verilogsystem-verilog
sundar
sundar

Reputation: 456

System Verilog Function return value as parameterized bit vector

I need to create a function in SystemVerilog with return value as a parameterized bit vector. My code is as follows:

class my_class #(parameter ADDR_WIDTH = 32);
    bit [ADDR_WIDTH-1:0] address;

    function bit [ADDR_WIDTH-1:0] get_address();
        return address;
    endfunction : get_address

endclass : my_class

I get a compile time error in the function declaration saying that the parameter ADDR_WIDTH is not defined. Can anyone please explain why this is happening? The same is working without the parameter (i.e if I have a known value like bit [31:0]).

Upvotes: 0

Views: 4959

Answers (1)

dave_59
dave_59

Reputation: 42748

There is nothing wrong with the code you showed in the original example, and I've tried it on earlier versions of Questa. Usually when you get unexplainable errors on code that looks perfectly fine, you are either using a version that is too old, or the real error is on a line above the the code in question.

Upvotes: 1

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