CODEWITHSUNDEEP
verilog
Patrick
Patrick

Reputation: 181

How to expand a single bit to multi-bits depending on parameter in verilog?

For example, I have an input wire fx, and parameter DATAWIDTH.

Can I write

wire [DATAWIDTH - 1 : 0] exfx;
assign exfx = {(DATAWIDTH - 1){1'b0}, fx};

to zero expand the signal fx to DATAWIDTH?

What if I want (DATAWIDTH - 1) bits 1? or more complex combination?

Upvotes: 3

Views: 16788

Answers (2)

Oldfart
Oldfart

Reputation: 6269

You are nearly there.

assign exfx = {{(DATAWIDTH-1){1'b0}}, fx};

This part: {(DATAWIDTH-1){1'b0}} are your extra zeros. Then you add those to fx using the { ... } operator.

This is 8 zero bits: {8{1'b0}}.
This is also 8 bits but the pattern 01010101 : {4{2'b01}}

The count can be an expression: {2*DATAWIDTH-1{1'b0}}

You can also use that to sign-extend a number by repeating the MS bit:

localparam WIDTH = 16;
wire       [7:0] A;
wire [WIDTH-1:0] B; 

// Works only for WIDTH > 8 !!
assign B = { {WIDTH-8{A[7]}} , A };

Upvotes: 8

kevin1494
kevin1494

Reputation: 158

Yes, you can do this. However, your exfx is of DATAWIDTH+1 size currently

A simple assign also works -

assign exfx = fx;

It will assign fx value to LSB and will have 0s in the rest

Upvotes: 0

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