CODEWITHSUNDEEP
vhdl
Ashwin
Ashwin

Reputation: 11

Can a PORT MAP be done in VHDL package body?

I am trying to do a PORT MAP inside a package body. I am not sure if it makes sense but i hope someone can tell me the logic there. Thank you

Upvotes: 0

Views: 264

Answers (3)

Martin Thompson
Martin Thompson

Reputation: 16832

PORT MAPs are used when you 'create' or 'instantiate' something "real" - like an adder for example.

Packages and package bodies hold only more abstract things like types, constants, procedures and functions. They can contain COMPONENTS, but a component declaration in VHDL is a bit like a datasheet - not the same as having the chip in your hand, it just tells you what the pins are called.

Upvotes: 0

user2778477
user2778477

Reputation:

No, you can not instantiate a component inside a package body.

legal Component instantiation placement:

Blk: BLOCK
  ...
BEGIN
  ...  <====
END BLOCK Blk;

and

ARCHITECTURE Arc OF Ent IS
  ...
BEGIN
  ...  <====
END ARCHITECTURE Arc;

Upvotes: 1

ice
ice

Reputation: 127

No, it is not possible to PORT MAP inside a package body.

PORT MAP, as the name implies, maps signals to the ports of the specified component. The component always have the same port name but the unit that is instantiating that particular component need not always have the same signal name. As a result, it is not logical to have PORT MAP clause inside a package which intends to be used by multiple units (files).

However, you can declare a component inside a package which eliminates the need to declare the same component every time you need to perform a PORT MAP. Functions and procedures are alternatives which you can do inside a package.

Upvotes: 0

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