CODEWITHSUNDEEP
vhdl
San
San

Reputation: 169

Can we include delays in structural architecture?

I am trying to simulate EXOR using NOR gates. I have written the following logic for EXOR gate. Now, my nor2 is defined with 4 ns delay. 

ENTITY ex IS
    PORT (a, b : IN BIT; c : OUT BIT);
END ex;

ARCHITECTURE structure OF ex IS

    SIGNAL tmp1, tmp2, tmp3, tmp4: BIT;
    COMPONENT nor2 PORT (x, y : IN BIT; z : OUT BIT); END COMPONENT;
BEGIN

    u0: nor2 PORT MAP (a, a, tmp1);

    u1: nor2 PORT MAP (b, b ,tmp2);

    u2: nor2 PORT MAP (tmp1,tmp2,tmp3);

    u3: nor2 PORT MAP (b, a, tmp4);

    u4: nor2 PORT MAP (tmp3, tmp4, c);

END structure;

I know that tmp1, tmp2 and tmp4 will change signals after 4 ns after a or b changes. I also notice that tmp3 and hence c change after 4 ns (because nor2 has 4 ns delay[c <= a nor b after 4ns]). But I want tmp3 to reflect the change after 8 ns as per the proper logic and c after 12 ns. This will give me the proper output for EXOR. My question is how do I introduce a delay in structural architecture? Is there a way to do it? I tried to search but did not find any and wait doesn't work, it keeps giving me syntax error (wait for 8ns). Thanks a lot for the help!

Upvotes: 0

Views: 705

Answers (2)

user2778477
user2778477

Reputation:

There is nothing wrong with the simulation result. It seems wrong because nor is a short-circuit operator.

Suppose that 

a = '0'
b = '1'

then 

tmp1 = '1' (a nor a)
tmp2 = '0' (b nor b)
tmp4 = '0' (b nor a)
tmp3 = '0' (tmp1 nor tmp2)
c    = '1' (tmp3 nor tmp4)

Now b changes to '0', 

tmp1 = '1' remains unchanged
tmp2 = '1' after 4 ns
tmp4 = '1' after 4 ns
tmp3 = '0' remains unchanged (regardless of b because of short-circuit evaluation)
c    = '0' after 8 ns (not 12 ns because it only waits for tmp4 in this case)

Upvotes: 1

user1155120
user1155120

Reputation:

You could convert your model to a VITAL compliant one (IEEE Std 1076.4 VITAL (VHDL Inititative Towards ASIC libraries) but that might be a bit overkill for your purposes. The standard characterizes the various types of delays, in this case combinatoric, where an output is dependent on a transition on an input.

For your top level model ex the delay on the c output is dependent on the longer of the delay from A to C or B to C. Note the VITAL standard also can track 0->1 delays separately from 1->0 delays.

Applying an abstract delay model for ex requires tracing delay paths through the various nor gates to calculate the A to C or B to C delays.

A VITAL compliant delay model allows you to apply Standard Delay Format (SDF) delay files to a design models with compliant tools much as generics apply timing or other model characterization.

For your purposes because you have characterized the delays through the various nor gates barring trace parasitics, you could use an intermediary value where C is output from the last nor gate now, and assign that to C after a delay controlled by A or B.

For characterizing delays, you can treat ex as a black box, providing delays at the macro level.

You appear to be anticipating no routing delays and symmetric 0->1 and 1->0 delays.

Something along the lines of an ordered list longer to shorter controlling delays

If A'event then C <= intermediary after AC_DELAY else intermediary after BC_DELAY; -- B'event

You can apply this at the finer level than macro, but it's not needed when individual nor gate outputs aren't used to determine some other output.

Upvotes: 0

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