CODEWITHSUNDEEP
vhdlverilogfpga
Liang He
Liang He

Reputation: 143

Does time delay in a sequential logic circuit block have a influence on synthesize or place or route's result？

I use Xilinx ISE as a IDE. If I add a 100 ps delay at every assignment in a always(Verilog)/process(VHDL) with sensitive list only have clock and reset. Like this.

always@(posedge clk)
    if(rst)
      a <= #100 'd0;
    else
      a <= #100 b;
    end

I think the delay function is only effect the simulation process.Because every book and user guide tell us delay is not synthesizable.

But I still wondering if the delay function can really effect the place or route's result?Like static timing or clock report? Like can make a circuit max frequency higher or slower?

Upvotes: 0

Views: 629

Answers (4)

user3885596
user3885596

Reputation:

"Usually" there is no impact on synthesis and P&R results.

Xilinx: This statement is usually ignored by the synthesis tool.

When does it have impact then?

Although the delay statement is ignored by the synthesis tool, the HDL code is a little bit different. That may change the seed of randomization in any stage (parsing, elaboration, synthesis etc.), so there is a possibility for different results. These results may be better or worse.

If a delay statement exists in the code, the following warning is expected from Xilinx ISE:

WARNING:Xst:916 - design.v line x: Delay is ignored for synthesis.

Upvotes: 0

Brian Magnuson
Brian Magnuson

Reputation: 1487

You are correct that there's nothing intrinsic about delay statements that makes them unsynthesizable, however it's wildly impractical to attempt to do so. The reason for this is that once on the FPGA you are dealing with a physical circuit whose performance varies with PVT (process, voltage, temperature) and can do so by a lot! The only hedge against this would be an analog circuit that attempts to sense all of the above and adjust itself accordingly. Such a beast will still be limited in what it can do, and would be physically large and power hungry depending on the rage of delay and the variance in all of the above you want to support.

So with than in mind and considering that there is very little (read: no) demand for this outside of special purpose IO FPGA vendors don't provide any such components making the construct unsythesizable.

Upvotes: 2

Alper Kucukkomurler
Alper Kucukkomurler

Reputation: 1794

Delay statements (#100) are usually ignored during synthesis in Verilog. So in synthesis it is the same as:

always@(posedge clk)
    if(rst)
      a <= 0;
    else
      a <= b;
    end

Xlinx Synthesis and Simuation Design Guide states:

Delays in Synthesis Code

Do not use Wait for XX ns (VHDL) or the #XX (Verilog) statements in your code. (...) This statement does not synthesize to a component. In designs that include this construct, the functionality of the simulated design does not always match the functionality of the synthesized design.

(...)

Wait for XX ns Statement Verilog Coding Example

#XX;

Do not use the After XX ns statement in your VHDL code or the Delay assignment in your Verilog code

(...)

Delay Assignment Verilog Coding Example

assign #XX Q=0;

XX specifies the number of nanoseconds that must pass before a condition is executed. This statement is usually ignored by the synthesis tool. In this case, the functionality of the simulated design does not match the functionality of the synthesized design.

Upvotes: 1

Prashant
Prashant

Reputation: 362

No the #delay in your code is not going to affect the timing of the design when it is loaded on to the FPGA.

It also does not affect the place and route results or the static timing analysis. Both of these steps use timing information that is provided by the manufacturer in the form of device models.

Upvotes: 3

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