CODEWITHSUNDEEP
vhdlmodelsim
Russell
Russell

Reputation: 3465

Weak 'H', Pullup on inout bidirectional signal in simulation

Is there a way to tell the simulator (I'm using Modelsim) to pull a signal to weak 'H' when it's not being driven by either bidirectional interface?

For example if I have an I2C signal I2C_SDA that is declared as an inout from 2 modules. One is my actual UUT and the other is a testbench. Both have statements like this:

io_i2c_sda <= r_I2C_DATA when r_I2C_DATA_EN = '1' else 'Z';

So both ends are tri-stated. This works fine in simulation, except that the line is BLUE ('Z') all the time that neither end is transmitting. How can I pull-up this line to a 'H' in the code when neither end is transmitting?

Upvotes: 5

Views: 12852

Answers (2)

Semnodime
Semnodime

Reputation: 2003

In modelsim (at least in Questa Sim 10.7c), you can manually drive a signal to any value (e.g. Z, or 1) via the wave pane:

This is equivalent to the vsim command force -drive sim:/testbench/UUT/…/i2c_master/sda 1 0.

Note that this method does not make driving the signal part of the RTL code though and has to be issued (e.g. by script) for every simulation.

modelsim_wave_view_drive_signal_high

Upvotes: 0

Yann Vernier
Yann Vernier

Reputation: 15887

For VHDL, it should be possible to simply add an extra driver to the signal (which has to be of std_logic type), with the constant value 'H'. In Verilog one would use a simple '1' driver and the net type wand for wired and. 'H' specifically means a weak high driver, so it will be overridden by the low drivers.

Upvotes: 5

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