JK Flip Flop Debugging Iteration Limit error in VHDL Modelsim

Question

I'm writing vhdl code for a jk-flip-flop on modelsim and i get an error when i try to simulate it: Error: Iteration limit reached at time 0 ns.

I'm not sure what it means, but I've looked through much of my source code for errors to no success. Can anyone guess what the problem might be?

library ieee;
use ieee.std_logic_1164.all;


entity SRlatch is
port(S,R:in bit; Q : inout bit ; QN : inout bit := '1');
end SRlatch;

architecture structural of SRlatch is
begin
Q <=  S nand QN;
QN <= R nand Q;
end;


entity JKFlipFlopStruct is
port(J,K,clk : in bit ; Q : inout bit ; QN : inout bit);
end JKFlipFlopStruct;

architecture structural of JKFlipFlopStruct is

  component SRlatch is
   port(S,R:in bit; Q : inout bit ; QN : inout bit := '1');
  end component;

  signal J0,K0,J1,K1,J2,K2 : bit;

begin

  J0 <= not ( J and QN and clk) );
  K0 <= not ( K and Q and clk) );

  f1 : SRlatch port map ( J0,K0,J1,K1 );

  J2 <= not ( J1 and (not clk) );
  K2 <= not ( K1 and (not clk) );
  f2 : SRlatch port map ( J2,K2,Q,QN );

end structural;

[JK Flop Flop negative edge triggered]

see image :https://i.sstatic.net/J3m1J.gif

Answer 1

library ieee;
use ieee.std_logic_1164.all;

entity SRlatch is
  port(S,R:in bit; Q : inout bit := '0' ; QN : inout bit := '1');
end SRlatch;

architecture structural of SRlatch is
begin
  Q <=  S nand QN;
  QN <= R nand Q;
end structural;

entity JKFlipFlopStruct is
  port(J,K,clk : in bit ; Q : inout bit ; QN : inout bit:= '1');
end JKFlipFlopStruct;

architecture structural of JKFlipFlopStruct is

  component SRlatch is
   port(S,R:in bit; Q : inout bit ; QN : inout bit := '1');
  end component;

  signal J1 : bit;
  signal J0,K0,K1,J2,K2 : bit:= '1';

begin

  J0 <= not ( J and QN and (not clk) );
  K0 <= not ( K and Q and (not clk) );

  f1 : SRlatch port map ( J0,K0,J1,K1 );

  J2 <= not ( J1 and clk );
  K2 <= not ( K1 and clk );

  f2 : SRlatch port map ( J2,K2,Q,QN );

end structural;

this is the correct code

Answer 2

As Russell say, this error usually indicates that ModelSim is stuck in an infinite loop. In VHDL, this can happen when a signal is placed in the sensitivity list and this signal is changed in the process.

A simple example:

process (sig)
begin
  sig <= not sig;
end;

Your problem is also in this case. But there are some differences.

1. For any concurrent signal assignment statement, there is an equivalent process statement with the same meaning. (See VHDL LRM 93 $9.5 for more details)

So, in your code,

J0 <= not ( J and QN and clk) );  

is short hand notation for

process
begin
   J0 <= not ( J and QN and clk) );
   wait on J, QN, clk;
end process;

or

process (J, QN, clk)
begin
    J0 <= not ( J and QN and clk) );
end process;

Others concurrent statements are the same.

2. About simulation cycle (See VHDL LRM 93 $12.6.4 and Delta Delays)
In eacy cycle, the values of all signals in the description are computed. If as a result of this computation an event occurs on a given signal, process statements that are sentitive to that signal will resume and will be executed as part of the simulation cycle.

In your code:

f2 : SRlatch port map ( J2,K2,Q,QN );

it's equivalent process:

process (J2, K2)
begin
   Q <=  J2 nand QN;
   QN <= K2 nand Q; 
end process;

along with other processes make an infinite loop.
For example,

the J-K Flip-Flop is stable @ 100 ns + 0 delta time
J or K or clk changes       @ 100 ns + 0 delta time
J0 or K0          \ ---
J1 or K1              |__ cost several delta times
J2 or K2              |   Suppose that Q changes @ 100 ns + 3 delta time
Q or QN  changes  / ---     
Then the value of K0 will change again!!
This result in a infinite loop becase 100 ns + n delta time = 100 ns. Time never advanceds.

Solutions:
1.Make your design a sequential one (ie. use a synchronic clock).

process (clk)
begin
    if (rising_edge(clk)) then
        -- signal assignment
    end if;
end process;  

2.Use delay assignment. So, in the SRlatch.vhd, you should write

Q <=  S nand QN after 1 ns;
QN <= R nand Q after 2 ns;

Unsymmetrical delay is used to ensure that either Q or QN sets up first and then feedbacks to set the other one.

Also refer to a similar question: Debugging Iteration Limit error in VHDL Modelsim.

Answer 3

Iteration limit means that you have created a feedback loop in your design and you made the simulator very angry! It cannot resolve the loop.

Use a clocked process to set J0 and K0.

jk_flippy_floppy : process (clk)
begin
  if rising_edge(clk) then
     J0 <= not ( J and QN );
     K0 <= not ( K and Q  );
  end if;
end process jk_flippy_floppy;