CODEWITHSUNDEEP
verilogsystem-veriloguvm
Jean
Jean

Reputation: 22745

How do I stop all running sequences in UVM?

Is there a way to stop all running sequences during a simulation(say when you get a reset) ? Is there a way to dump the a list of all running sequences at particular time during simulation ?

Upvotes: 1

Views: 11139

Answers (2)

Dheerendra Tiwari
Dheerendra Tiwari

Reputation: 11

There is a bit received_item_done in every sequence. You can wait for the posedge of this bit before stopping any particular sequence. You can use the current_grabber function from the sequencer base class to get a handle of the sequence which currently has a lock or grab on the sequence.

stop_sequences will stop the sequence currently loaded on a sequencer.

Upvotes: 1

dave_59
dave_59

Reputation: 42788

Yes. sequencer_h.stop_sequences() See https://verificationacademy.com/cookbook/Sequences/Stopping for what you need to do and what you need to be careful about with an active driver.

There is nothing built-in to the UVM to dump all the running sequences, but if you are using Questa, there is a debugging command "uvm findsequences" that will list them out for you.

Upvotes: 4

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