CODEWITHSUNDEEP
verilogperiodic-task
Sangeet Saha
Sangeet Saha

Reputation: 83

creating periodic tasks set in verilog

I want to create a set of periodic tasks set with different period and execution time, in verilog module, that task will create so will operate some sorts of operation and shall be executed after certain periods...

So, In higher level language like in c

func()
{
for(;;)
}
and sleep()

I think, i would use that func() as operation and after sleep()..this func() shall be called again... is this a right way to do so in verilog?? and Can I also measure the execution time as well as period in testbench...after simulation.. any suggestion would be highly helpful

regards

Upvotes: 0

Views: 738

Answers (1)

mcleod_ideafix
mcleod_ideafix

Reputation: 11418

Something like...

`timescale 1ns/1ns
always begin
  // do stuff
  # amount of nanoseconds to wait until next execution
end

For example: this periodic task increments variable counter every 1.5 microsecond.

`timescale 1ns/1ns
integer counter = 0;
always begin
  counter = counter + 1;
  #1500;
end

Use `timescale with different units if you don't need nanosecond precision. For example, the previous block could be written as this:

`timescale 1us/1ns
integer counter = 0;
always begin
  counter = counter + 1;
  #1.5;
end

EDIT

It is important to make clear that simulated delays, denoted by #{insert_delay}, cannot be synthesized. They should only be used in a test bench to model delays coming from a driver. So of your func() and sleep() are not in a testbench, they will need to be modeled as some sort of counter, that resets then counts x number of clock pulses.

Upvotes: 1

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