CODEWITHSUNDEEP
taskverilogiverilog
AnnaR
AnnaR

Reputation: 361

How to call tasks from a separate module in Verilog?

I'm new to Verilog and would really appreciate it if someone could help me with this.

I have a task written in a separate file - "task.v" :

module task_create();

task assign_inp;
    reg a,b,c,d;
    //details
endtask

endmodule

I have a module that is calling this task: 

module tb();
    `include "task.v"
    assign_inp(a,b,c,d);
endmodule

When I execute this, I get this error:

Module definition task_create cannot nest into module tb

When I remove the module and endmodule in task.v, I get this error:

Task must be contained inside a module

Where am I going wrong? Thank you so much!

Upvotes: 1

Views: 5793

Answers (1)

okebz
okebz

Reputation: 152

Your task is in a module and so can only be seen in the module. You can remove the module wrapper and just declare the task in a separate file.

task assign_inp;
    reg a,b,c,d;
    //details
endtask

You can include the task, and you should be able to see the task.

Removing the modules works for me.

You may need to declare the Verilog file as a header file for the task

Upvotes: 2

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