Not displaying waveforms in simulation without errors

Question

I wrote a code for 16-bit ALU in both behavioral and RTL model. It doesn't have any compilation or simulation errors, but when I hit the run button in the waveform window it is not displaying any of the inputs or outputs not even clock.

Here is the test bench I created for it:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
Use IEEE.NUMERIC_STD.UNSIGNED;

use ieee.std_logic_textio.all;
USE WORK.ANU.ALL;

entity xalu_tb is
end xalu_tb;

architecture beh of xalu_tb is

  component bitalu
    Port (A, B, CIN              : in  STD_LOGIC_VECTOR(15 DOWNTO 0);
          CLK, RST               : IN  STD_LOGIC;
          OPCODE                 :     OPCODE1;
          RES                    : OUT STD_LOGIC_VECTOR (31 downto 0);
          CARRY, GT, LT, EQ, NEQ : OUT STD_LOGIC
          );
  end component;
  component alurtl
    port
      (
        data1, data2                    : in  std_logic_vector(15 downto 0);
        operation                       : in  bit_vector(3 downto 0);
        result                          : out std_logic_vector(31 downto 0);
        carry1, equal, nequal, grt, lrt : out std_logic
        );
  end component;
  signal A, B, CIN                       : STD_LOGIC_VECTOR(15 DOWNTO 0);
  signal clk, rst                        : STD_LOGIC;
  signal opcode                          : opcode1;
  signal res                             : STD_LOGIC_VECTOR (31 downto 0);
  signal CARRY, GT, LT, EQ, NEQ          : STD_LOGIC;
  signal data1, data2                    : std_logic_vector(15 downto 0);
  signal operation                       : bit_vector(3 downto 0);
  signal result                          : std_logic_vector(31 downto 0);
  signal carry1, equal, nequal, grt, lrt : std_logic;

  file InFile  : text open read_mode is "C:/Users/---/Desktop/response.txt";
  file OutFile : text open write_mode is "C:/Users/---/Desktop/response1.txt";
begin
  u_x : bitalu port map(A, B, CIN, CLK, RST, OPCODE, RES, CARRY, GT, LT, EQ, NEQ);

  u_xx : alurtl port map(data1, data2, operation, result, carry1, equal, nequal, grt, lrt);

  A     <= "0000000000001010";
  B     <= "0000000000000110";
  CIN   <= "0000000000000000";
  DATA1 <= "0000000000001010";
  DATA2 <= "0000000000000110";

  CREATE_CLOCK : process
  begin
    if (rst <= '1') then
      res    <= "00000000000000000000000000000000";
      result <= "00000000000000000000000000000000";
    else
      clk <= '1';
      wait for 5 ns;
      clk <= '0';
      wait for 5 ns;
    end if;
  end process;

  p1 : process
    variable res                                      : std_logic_vector(31 downto 0);
    variable result                                   : std_logic_vector(31 downto 0);
    variable lt, gt, eq, neq, lrt, grt, equal, nequal : std_logic;
    variable L1, L2                                   : line;

  begin
    wait until clk = '1' and clk'event;

    OPCODE    <= ADD;
    operation <= "0000";
    if(not (endfile(infile))) then
      readLine(infile, L1);
      readLine(infile, L2);
      read(L1, res);
      read(L2, result);
      assert(res(15 downto 0) = result(15 downto 0)) report "notmatch"severity error;
      write(L1, RES);
      writeline(outfile, L1);
      write(L2, result);
      writeline(outfile, L2);
    end if;
    wait for 10 ns;

    OPCODE    <= sub;
    operation <= "0001";
    if(not (endfile(infile))) then
      readLine(infile, L1);
      readLine(infile, L2);
      read(L1, res);
      read(L2, result);
      assert(res(15 downto 0) = result(15 downto 0)) report "notmatch"severity error;
      write(L1, RES);
      writeline(outfile, L1);
      write(L2, result);
      writeline(outfile, L2);
    end if;
    wait for 10 ns;
    OPCODE    <= mul;
    operation <= "0010";
    if(not (endfile(infile))) then
      readLine(infile, L1);
      readLine(infile, L2);
      read(L1, res);
      read(L2, result);
      assert(res(15 downto 0) = result(15 downto 0)) report "notmatch"severity error;
      write(L1, RES);
      writeline(outfile, L1);
      write(L2, result);
      writeline(outfile, L2);
    end if;
    wait for 10 ns;
    OPCODE    <= comp;
    operation <= "0011";
    if(res(16) = '1') then
      if(not (endfile(infile))) then
        readLine(infile, L1);
        readLine(infile, L2);
        read(L1, lt);
        read(L2, lrt);
        assert(lt = lrt) report "notmatch"severity error;
        write(L1, lt);
        writeline(outfile, L1);
      end if;
    elsif(res = "0000000000000000") then
      if(not (endfile(infile))) then
        readLine(infile, L1);
        readLine(infile, L2);
        read(L1, eq);
        read(L2, equal);
        assert(eq = equal) report "notmatch"severity error;
        write(L1, eq);
        writeline(outfile, L1);
      end if;
    else
      if(not (endfile(infile))) then
        readLine(infile, L1);
        readLine(infile, L2);
        read(L1, gt);
        read(L2, grt);
        assert(gt = grt) report "notmatch"severity error;
        write(L1, gt);
        writeline(outfile, L1);
      end if;
    end if;

    wait for 10ns;
    OPCODE    <= and16;
    operation <= "0100";
    if(not (endfile(infile))) then
      readLine(infile, L1);
      readLine(infile, L2);
      read(L1, res);
      read(L2, result);
      assert(res(15 downto 0) = result(15 downto 0)) report "notmatch"severity error;
      write(L1, RES);
      writeline(outfile, L1);
      write(L2, result);
      writeline(outfile, L1);
    end if;

    wait for 10 ns;
    OPCODE    <= or16;
    operation <= "0101";
    if(not (endfile(infile))) then
      readLine(infile, L1);
      readLine(infile, L2);
      read(L1, res);
      read(L2, result);
      assert(res(15 downto 0) = result(15 downto 0)) report "notmatch"severity error;
      write(L1, RES);
      writeline(outfile, L1);
      write(L2, result);
      writeline(outfile, L2);
    end if;

    wait for 10 ns;
    OPCODE    <= not16;
    operation <= "0110";
    if(not (endfile(infile))) then
      readLine(infile, L1);
      readLine(infile, L2);
      read(L1, res);
      read(L2, result);
      assert(res(15 downto 0) = result(15 downto 0)) report "notmatch"severity error;
      write(L1, RES);
      writeline(outfile, L1);
      write(L2, result);
      writeline(outfile, L2);
    end if;

    wait for 10 ns;
    OPCODE    <= xor16;
    operation <= "0111";
    if(not (endfile(infile))) then
      readLine(infile, L1);
      readLine(infile, L2);
      read(L1, res);
      read(L2, result);
      assert(res(15 downto 0) = result(15 downto 0)) report "notmatch"severity error;
      write(L1, RES);
      writeline(outfile, L1);
      write(L2, result);
      writeline(outfile, L2);
    end if;


    wait for 10 ns;
    OPCODE    <= srl16;
    operation <= "1000";
    if(not (endfile(infile))) then
      readLine(infile, L1);
      readLine(infile, L2);
      read(L1, res);
      read(L2, result);
      assert(res(15 downto 0) = result(15 downto 0)) report "notmatch"severity error;
      write(L1, RES);
      writeline(outfile, L1);
      write(L2, result);
      writeline(outfile, L1);
    end if;

    wait for 10 ns;
    OPCODE    <= sll16;
    operation <= "1001";
    if(not (endfile(infile))) then
      readLine(infile, L1);
      readLine(infile, L2);
      read(L1, res);
      read(L2, result);
      assert(res(15 downto 0) = result(15 downto 0)) report "notmatch"severity error;
      write(L1, RES);
      writeline(outfile, L1);
      write(L2, result);
      writeline(outfile, L2);
    end if;

    wait for 10 ns;
    OPCODE    <= sra16;
    operation <= "1010";
    if(not (endfile(infile))) then
      readLine(infile, L1);
      readLine(infile, L2);
      read(L1, res);
      read(L2, result);
      assert(res(15 downto 0) = result(15 downto 0)) report "notmatch"severity error;
      write(L1, RES);
      writeline(outfile, L1);
      write(L2, result);
      writeline(outfile, L2);
    end if;

    wait for 10 ns;
    operation <= "1011";
    OPCODE    <= sla16;
    if(not (endfile(infile))) then
      readLine(infile, L1);
      readLine(infile, L2);
      read(L1, res);
      read(L2, result);
      assert(res(15 downto 0) = result(15 downto 0)) report "notmatch"severity error;
      write(L1, RES);
      writeline(outfile, L1);
      write(L2, result);
      writeline(outfile, L2);


    end if;
    wait for 10 ns;

  end process;

end beh;

Answer 1

yes you are right the mistake is that I made an signal assignment i.e if res<=1 this statement is executing as infinite loop .Because it is considering "<= " as less than or equal. thank you very much this fixed everything

Answer 2

I read the example as far as:

  CREATE_CLOCK : process
  begin
    if (rst <= '1') then

Now the token <= has two meanings which are unambiguous because they can be distinguished according to context...

The first is as a signal assignment statement. Not "assignment operator" because unlike some languages, assignment is not an operator. Therefore there can be no confusion between rst <= '1'; and if rst <= '1' then.

The second meaning - in an expression - is a relational operator "less than or equal". And that is what you have implemented above. So the circuit will stay in reset and never advance the clock, until rst > '1' (i.e. never).

A separate problem is that the process is not sensitive to changes on Rst (or anything else!) so it will never wake up...

Try

  CREATE_CLOCK : process (rst)
  begin
    if rst = '1' then

At least it will allow the circuit to come out of reset...

A few other comments :

1. Lose the non-standard library use clauses and use numeric_std instead...

   use IEEE.std_logic_arith.all;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

2. You don't need parentheses around boolean expressions. They are just clutter, possibly inherited from C. The following are equivalent:

   if(not (endfile(infile))) then
if not endfile(infile) then

3. The repetitive testbench code can be improved by pasting the common part into a procedure and calling it several times. If it's declared local to the process (after the variable declarations) it can see all the process state, or you can pass it any arguments you want.

4. It looks as if opcode and operation might be duplicates or have the same function. If so it would be a good idea to eliminate one (preferably "operation") or at least tie them together : for example constant operations : array(Opcode1) of std_logic_vector(3 downto 0) := (
Add => "0000",
Sub => "0001", ... );

   operation <= operations(Opcode);

Answer 3

Reason is this test bench code part:

CREATE_CLOCK : process
begin
  if (rst <= '1') then
    res    <= "00000000000000000000000000000000";
    result <= "00000000000000000000000000000000";
  else
    ... (code with wait statement)
  end if;
end process;

The process will repeatedly execute at the same simulation time and delta when rst <= '1' is initially TRUE, since a wait statement is never executed. The simulation will therefore never advance. Code must be fixed to ensure that a wait statement is executed in the process.

Elaboration:

If the simulation time and delta does not advance, for example stays at:

Now: 0 ps Delta: 0

or some later time and delta, then the reason may be a process without a sensitivity list where the wait is never executed, like:

process is
begin
  if FALSE then
    wait;
    ...

or an endless loop like:

while TRUE loop
  ...

ModelSim will not report any warnings (as "Possible infinite loop: Process contains no WAIT statement.") or error for code like the above, and the simulator may even be pretty difficult to stop through stop and break GUI interaction.