CODEWITHSUNDEEP
vhdlsimulationvivado
Sami
Sami

Reputation: 417

I am unable to find error in my simulation file of VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity test_adder_vhdl is
end test_adder_vhdl;

architecture Behavioral of test_adder_vhdl is
constant clock_period : time := 1000 ns ;
component adder is
PORT (A: in STD_LOGIC;
     B: in STD_LOGIC;
     SUM: out STD_LOGIC;
     CARRY: out STD_LOGIC);
end component adder;

SIGNAL A: STD_LOGIC : ='0';
SIGNAL B: STD_LOGIC : ='0';
SIGNAL SUM: STD_LOGIC : ='0';
SIGNAL CARRY: STD_LOGIC : ='0';
begin

uut: adder port map(
A=> A;
B=> B;
SUM => SUM;
CARRY => CARRY;
);

clk gena: process
begin
wait for 100 ns;
A <= not A;
end process;

clk genb: process
begin
wait for 50 ns;
B <= not B;
end process;
end Behavioral;

The error in the above code is

[HDL 9-806] Syntax error near ":". ["F:/practiceWorkspace/practice1/practice1.srcs/sim_1/new/test_adder_vhdl.vhd":38]

Upvotes: 0

Views: 1045

Answers (1)

user1155120
user1155120

Reputation:

You are not showing line number correspondence with your design. The error appears to correspond with the signal declaration for A. There are more syntax errors.

Statements are delimited by a semicolon. Interface declarations are separated by semicolons. Other object declarations are delimited by semicolons. Multiple elements (in the association list here) are separated by commas.

There are four signal declarations (A, B, SUM, CARRY) with extraneous spaces between the ':' and '=' in the compound delimiter ":=" used to providing a default value of '0'.

These should be: 

SIGNAL A: STD_LOGIC := '0';
SIGNAL B: STD_LOGIC := '0';
SIGNAL SUM: STD_LOGIC := '0';
SIGNAL CARRY: STD_LOGIC := '0';

:= is a used to signify variable assignment, values for constants and default expressions (values) for objects.

In the port map ',' should be used as a separator in the association list instead of ';'. 

uut: adder port map (
A=> A,
B=> B,
SUM => SUM,
CARRY => CARRY  -- NO TRAILING SEPARATOR
);

The last association does not require a following comma (a delimiter used as a separator).

There's a space instead of an underscore in the labels clk_gena and clk_genb.

clk_gena: process
begin
wait for 100 ns;
A <= not A;
end process;

clk_genb: process
begin
wait for 50 ns;
B <= not B;
end process;

A label is a single identifier consisting of a letter followed by one or more letters or numbers separated by zero or one underscore characters. The processes are labelled (named) clk_gena and clk_genb.

After fixing these your code analyzes (compiles). Without the entity and architecture pair for component adder your code can't be elaborated (linked) or simulated.

Note that the two processes suspend for 50 ns, and a process without an implicit last wait statement waiting on elements of a sensitivity list will merrily start executing the first sequential statement of the process after executing the last.

The expectation would be that you'd either add a trailing wait statement or control simulation by an implementation dependent method (e.g. run for some simulation time interval).

Your constant clock_period is not used (as yet) in your testbench.

Upvotes: 2

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