CODEWITHSUNDEEP
syntax-errorvhdlhdlvivado
NDEthos
NDEthos

Reputation: 516

Getting "No such design unit" from Vivado

I need someone to check my code and give me a sanity check. This is written in VHDL. Vivado keeps complaining the error:

[Synth 8-493] no such design unit 'onesevenseg'

But, I can clearly see the file in my project and the project manager source window is listing the files in the proper way.

This is the line where the error occurs.

digitOne: entity xil_defaultlib.oneSevenSeg port map (switchIn, sevenSegOut);

Here is the top level file that has the error. It is compiled into the library xil_defaultlib.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity oneSevenSegTop is
    Port ( anodeOut : out STD_LOGIC_VECTOR (0 to 7);
           switchIn : in STD_LOGIC_VECTOR (0 to 3);
           sevenSegOut : out STD_LOGIC_VECTOR (0 to 6));
end oneSevenSegTop;

architecture Behavioral of oneSevenSegTop is
component oneSevenSeg 
    Port ( digitIn : in STD_LOGIC_VECTOR (0 to 3);
           segOut : out STD_LOGIC_VECTOR (0 to 6));
end component;
begin

digitOne: entity xil_defaultlib.oneSevenSeg port map (switchIn, sevenSegOut);

anodeOut <= "00000001";

end Behavioral;

Here is the file that is being instantiated by the above file, also compiled into the library xil_defaultlib.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity oneSevenSeg is
    Port ( digitIn : in STD_LOGIC_VECTOR (0 to 3);
           segOut : out STD_LOGIC_VECTOR (0 to 6));
end oneSevenSeg;

architecture Behavioral of oneSevenSeg is

begin
process(digitIn)
begin
if digitIn = "0000" then --0
    segOut <= "1000000";
elsif digitIn = "0001" then --1
    segOut <= "1111001";
elsif digitIn = "0010" then --2
    segOut <= "0100100";
elsif digitIn = "0011" then --3
    segOut <= "0110000";
elsif digitIn = "0100" then --4
    segOut <= "0011001";
elsif digitIn = "0101" then --5
    segOut <= "0010010";
elsif digitIn = "0110" then --6
    segOut <= "0000010";
elsif digitIn = "0111" then --7
    segOut <= "1111000";
elsif digitIn = "1000" then --8
    segOut <= "0000000";
elsif digitIn = "1001" then --9
    segOut <= "0011000";
else                   -- error
    segOut <= "0110110";
end if;

end process;

end Behavioral;

Upvotes: 1

Views: 4125

Answers (2)

scary_jeff
scary_jeff

Reputation: 4374

Although the answer from @user1155120 is correct, the underlying problem here is that you're not referencing the entity in the intended way. The xil_defaultlib is the name of the library that Xilinx Vivado compiles your design into by default. You do not need to reference this at all, instead, make use of the idea that work is used to refer to the library currently being compiled:

digitOne: entity work.oneSevenSeg port map (switchIn, sevenSegOut);

In this way, your code is not tied to the specific way that Vivado decides to compile your project. It doesn't make sense to add references to xil_defaultlib throughout your code when you could more easily use the work method.

Upvotes: 0

user1155120
user1155120

Reputation:

Trying your two files with ghdl:

% ghdl -a --work=xil_defaultlib onesevenseg.vhdl
% ghdl -a -P. onesevensegtop.vhdl
onesevensegtop.vhdl:17:18: no declaration for "xil_defaultlib"
ghdl: compilation error

So the second listed design unit from the question analyzed fine into a new working library named xil_defaultlib.

The second analysis is for the top level unit and the -P flag tells it to look in the current location for additional libraries.

And that analysis failed, because the name xil_defaultlib hasn't been declared.

IEEE Std 1076-2008, 13.2 Design libraries:

A library clause defines logical names for design libraries in the host environment. A library clause appears as part of a context clause, either at the beginning of a design unit or within a context declaration.
...
Each logical name defined by the library clause denotes a design library in the host environment.

Without telling the analyzer that the simple name xil_defaultlib references a library in the host environment the meaning of the name is unknown.

If the prefix isn't a library logical name then it must be a design unit, but the name isn't known in library work, library IEEE or library std:

12.3 Visibility:

Visibility is either by selection or direct. A declaration is visible by selection at places that are defined as follows:

a) For a primary unit contained in a library: at the place of the suffix in a selected name whose prefix denotes the library.

Further in 13.2:

Every design unit except a context declaration and package STANDARD is assumed to contain the following implicit context items as part of its context clause:

library STD, WORK; use STD.STANDARD.all;

Notice library logical names can be defined implicitly as well as explicitly. There is no implicit definition for xil_defaultlib.

Add a library clause making the prefix of the selected name xil_defaultlib.oneSevenSeg visible.

This can be done right up there with the library clause making the library logical name IEEE visible in the unnamed top level file:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library xil_defaultlib;

entity oneSevenSegTop is
...

So we make that change and:

% ghdl -a -P. onesevensegtop.vhdl
%

No errors.

Upvotes: 3

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