How to create port map that maps a single signal to 1 bit of a std_logic_vector?

Question

I am designing some hardware using VHDL. My design requires the use of a 12-bit ripple counter that will utimately get connected as shown in the schematic screenshot below.

I found an existing entity & architecture for a ripple counter from online that I have decided should be suitable for my design. Here it is, in case it is useful in helping answer my question.

entity ripple_counter is
    generic (
        n : integer := 12
    );
    port (
        clk   : in std_logic;
        clear : in std_logic;
        dout  : out std_logic_vector(n-1 downto 0)
    );
end ripple_counter;

architecture behavioral of ripple_counter is

    signal clk_i, q_i : std_logic_vector(n-1 downto 0);

begin
    clk_i(0) <= clk;
    clk_i(n-1 downto 1) <= q_i(n-2 downto 0);

    gen_cnt: for i in 0 to n-1 generate
        dff: process(clear, clk_i)
        begin
            if (clear = '1') then
                q_i(i) <= '1';
            elsif (clk_i(i)'event and clk_i(i) = '1') then
                q_i(i) <= not q_i(i);
            end if;
            end process dff;
    end generate;
    dout <= not q_i;
end behavioral;

One will see that the ripple counter entity uses a n-bit (12-bit in this case) std_logic_vector for it's output. But, only two of the Q* outputs get connected. The ripple counter's component and port map declarations have been created as follows. Note that u22d_out, u21b_out and, u26_q12_out are all signals that have been defined in the same structural architecture as the ripple counter's component and port map. Also, q10 is an output of the system.

component ripple_counter is
    generic (
        n : integer := 12
    );
    port (
        clk   : in std_logic;
        clear : in std_logic;
        dout  : out std_logic_vector(n-1 downto 0)
    );
end component;

u26: ripple_counter port map (
    clk => u22d_out,
    clear => u21b_out,
    dout(11) => u26_q12_out,
    dout(9) => q10
);

When I attempt to run my design I get the following errors...

Error: [42972]: "c:/somefilepath/somefilename.vhd", line 493: Incomplete sub-element association for formal dout

Error: [42604]: "c:/somefilepath/somefilename.vhd", line 489: Port and Port Map does not match

Error: [40008]: HDL analysis failed.

• Line 493 is the line that reads dout(9) => q10.
• Line 489 is the line that reads u26: ripple_counter port map.

I am unsure if this is a syntax error or if it is a functional issue. How can I map specific bits of a vector to a single signal?

Answer 1

As suggested by Brian D in the comments...the port map association was incomplete. Here is an updated version of the port map.

u26: ripple_counter port map (
    clk => u22d_out,
    clear => u21b_out,
    dout(11) => u26_q12_out,
    dout(10) => open,
    dout(9) => q10,
    dout(8 downto 0) => open
);