CODEWITHSUNDEEP
makefile
Piyush Kumar
Piyush Kumar

Reputation: 167

Makefile including another make file?

I have to create a make file and it is dependent on some other make file. Now , the other file defines the targets. So I am asking whether I can have targets in both the files or not.

TARGET = 0

ifeq ($(TARGET),0) CC = gcc CFLAGS = -g -lpthread -lrt -O3 -Wall -lm else CC=arm-v7a15v3r1-linux-gnueabi-gcc CFLAGS = -lpthread -lrt -O3 -g -mcpu=cortex-a9 -ftree-vectorize endif

PNG_INC_DIR = lpng167/inc ZLIB_INC_DIR = zlib128/inc

DEFINES = -DZ_SOLO

pngsrc = lpng167/src/png.c\ lpng167/src/pngerror.c\ lpng167/src/pngget.c\ lpng167/src/pngmem.c\ lpng167/src/pngpread.c\ lpng167/src/pngread.c\ lpng167/src/pngrio.c\ lpng167/src/pngrtran.c\ lpng167/src/pngrutil.c\ lpng167/src/pngset.c\ lpng167/src/pngtrans.c

zlibsrc = zlib128/src/adler32.c\ zlib128/src/crc32.c\ zlib128/src/infback.c\ zlib128/src/inffast.c\ zlib128/src/inflate.c\ zlib128/src/inftrees.c\ zlib128/src/uncompr.c\ zlib128/src/zutil.c

testsrc = lpng167/src/pngtest.c

PNGOBJS = $(pngsrc:.c=.o) ZLIBOBJS = $(zlibsrc:.c=.o) TESTOBJS = $(testsrc:.c=.o) EXE = pngtest

all: $(EXE)

$(EXE):$(ZLIBOBJS) $(PNGOBJS) $(TESTOBJS) $(CC) $(CFLAGS) $(DEFINES) $(PNGOBJS) $(TESTOBJS) $(ZLIBOBJS) -o $(EXE)

%.o : %.c $(PNG_INC_DIR)/*.h $(ZLIB_INC_DIR)/*.h @echo $< @$(CC) $(CFLAGS) -I$(PNG_INC_DIR) -I$(ZLIB_INC_DIR) $(DEFINES) -c $< -o $@

.PHONY: clean clean: -@$(RM) -f $(ZLIBOBJS) $(PNGOBJS) $(TESTOBJS) $(EXE) 2> /dev/null

This is the first make file which defines its own targets. the other make file is a system make file thats too big too format , that defines dynamic targets according to the machine type. This is the link. The current make file which has no targets is EXECUTABLE := subM CCFILES := SubFilHost.cpp include ../../common/common_opencl.mk

I am really new to this make file thing, and the more I try to get this, the more it confuses. Any help would be grateful; Thanks Piyush

Upvotes: 1

Views: 166

Answers (1)

John
John

Reputation: 3520

Including a makefile is the same as cutting and pasting the contents of that makefile into the current makefile. So you can have targets in both makefiles as long as they don't conflict. You can only have one recipe per static target per makefile. However, you can define a target with just prerequisites as many times as you like. So you can do:

foo: bar1

foo: bar2
     echo "hello world"

You cannot do:

foo:
    echo "hello world1"

foo:
    echo "hello world2"

(Ok, you can, but make spits out some warnings, and only runs the last rule). For pattern rules, you can have a pattern rule and a static rule which would resolve to the same target. So, you could do:

%.o: %.c
    echo "used pattern rule"

foo.o: foo.c
    echo "used static rule"

In this case, make would run the best match -- which would be the static rule for foo.c. You can also have multiple patterns which overlap a target, and make will not complain. In this case, make runs the best match only.

John

Upvotes: 1

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