CODEWITHSUNDEEP
linuxbashshellmakefile
Kasper
Kasper

Reputation: 690

Common "include" file between shell and makefile

I've created an (makefiles oriented) include file which contains some variables defined to be used on by others makefiles.

# this is myinclude/makevars file
MY_FOLDER:=$(ROOT_FOLDER)/my/folder
ANOTHER_FOLDER:=$(MY_FOLDER)/another/folder
MY_LIB:=$(ANOTHER_FOLDER)/lib

this "include file" works just great if I include it in other makefiles: 

include myinclude/makevars

but would be cool if I might include it in some shell script too!. Currently I've created another file (myinclude/shellvars) very similar but "shell" oriented: 

# this is myinclude/shellvars file
MY_FOLDER=$ROOT_FOLDER/my/folder
ANOTHER_FOLDER=$MY_FOLDER/another/folder
MY_LIB=$ANOTHER_FOLDER/lib

clearly by including this in my (shell) scripts anything works but I have a duplicated file with (semantically) the same info!

any idea to have this two files "merged" into one (myinclude/makevars and myinclude/shellvars) ? any special syntax? any help is clearly appreciated!

-- kasper!

Upvotes: 0

Views: 230

Answers (1)

hidefromkgb
hidefromkgb

Reputation: 5904

Try this:

eval "$(cat makevars.inc | tr -d '(:)')"
echo "$MY_LIB"

This loads the text of the target include file into memory, erases all colons and parentheses from it and then executes the result.

Upvotes: 2

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