CODEWITHSUNDEEP
verilog
Gouse Shaik
Gouse Shaik

Reputation: 338

JK flipflop code in verilog using structural

i am writing an verilog program for jk flipflop in structural level my program is as follows:

module jkstruct(j,k,clk,q,qbar);

input j,k,clk;

output reg q,qbar;

initial begin q=1'b1;qbar=1'b0; end

wire x,y,w,z;

assign w=q;

assign z=qbar;

nand n1(x,z,j,clk);

nand n2(y,k,w,clk);

nand n3(q,x,z);

nand n4(qbar,y,w);

endmodule

ERROOR:Simulator:754 - Signal EXCEPTION_ACCESS_VIOLATION receivedPrinting stacktrace...

was appearing on simulator error panel. I am using xilinx 13.4 licensed version.

Upvotes: 1

Views: 14821

Answers (1)

Morgan
Morgan

Reputation: 20514

You are initialising outputs with 

initial begin q=1'b1;qbar=1'b0; end

When they are combinatorially driven from :

nand n3(q,x,z);
nand n4(qbar,y,w);

The above requires the output to be connected via wire not reg.

Remove the initial, and reg declaration (apply change to below), and report back if the issue still persists.

output q,qbar; // was output reg q,qbar;

Upvotes: 1

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