CODEWITHSUNDEEP
vhdl
user3491815
user3491815

Reputation: 31

What is the need for a sensitivity list to be associated with a process declaration? Can you declare a clocked process without a sensitivity list?

What is the need for a sensitivity list to be associated with a process declaration? Can you declare a clocked process without a sensitivity list?

Upvotes: 3

Views: 4918

Answers (3)

user1155120
user1155120

Reputation:

What is the need for a sensitivity list to be associated with a process declaration?

There's some information describing the relationship between concurrent statements and processes; processes, sensitivity lists and wait statements.

From IEEE Std 1076-2008 IEEE Standard VHDL Language Reference Manual

11. Concurrent statements, 11.1 General

Concurrent statements are used to define interconnected blocks and processes that jointly describe the overall behavior or structure of a design.

11.3 Process statement

If a process sensitivity list appears following the reserved word process, then the process statement is assumed to contain an implicit wait statement as the last statement of the process statement part; this implicit wait statement is of the form wait on sensitivity_list ;

and

If a process sensitivity list appears following the reserved word process in a process statement, then the process statement shall not contain an explicit wait statement.

10.2 Wait statement

wait_statement ::=
    [ label : ] wait [ sensitivity_clause ] [ condition_clause ] [ timeout_clause ] ;
sensitivity_clause ::= on sensitivity_list
sensitivity_list ::= signal_name { , signal_name }
condition_clause ::= until condition
condition ::= expression
timeout_clause ::= for time_expression

The wait statement causes the suspension of a process statement or a procedure.

The condition clause specifies a condition that shall be met for the process to continue execution. If no condition clause appears, the condition clause until TRUE is assumed.

The timeout clause specifies the maximum amount of time the process will remain suspended at this wait statement. If no timeout clause appears, the timeout clause for (STD.STANDARD.TIME'HIGH – STD.STANDARD.NOW) is assumed.

The suspended process also resumes as a result of an event occurring on any signal in the sensitivity set of the wait statement. If such an event occurs, the condition in the condition clause is evaluated. If the value of the condition is FALSE, the process suspends again. Such repeated suspension does not involve the recalculation of the timeout interval.

11.1

The primary concurrent statements are the block statement, which groups together other concurrent statements, and the process statement, which represents a single independent sequential process. Additional concurrent statements provide convenient syntax for representing simple, commonly occurring forms of processes, as well as for representing structural decomposition and regular descriptions.

A process either contains a sensitivity list providing an implicit wait statement as the last statement or explicit wait statement(s). Processes suspend and resume executing wait statements. Processes without wait statements will not allow design model execution to proceed - every process is executed at least one during simulation initialization (14.7.5.2).

Can you declare a clocked process without a sensitivity list?

Yes. For all practical purposes such a process must contain a wait statement. IEEE Std 1076.6-2004 IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis (now withdrawn) section 6. Modeling hardware elements, 6.1 Edge-sensitive sequential logic and it's subclauses describe the forms for clocked assignment. Even today with the standard withdrawn all VHDL synthesis tools still support these forms while generally describing 'preferred' forms in their documentation.

The essential requirement is wait statement (implied or explicit) with a signal used as a clock in it's sensitivity list and evaluating an edge transition on a clock (as opposed to a enable level for a latch).

Because concurrent statements performing assignments represent processes with an equivalent sequence of statements a concurrent conditional signal assignment statement can be used to describe sequential logic (6.1.3.5 Edge-sensitive storage using concurrent signal assignment statements).

There are two common forms of clock edge conditional evaluation, determining there is an event on the signal used as a clock and detecting it's current value (e.g. clk'event and clk = '1') or using functions detection transitions from one binary state to the other using signal'last (rising_edge(clk), falling_edge(clk)).

There can be synthesis restrictions on the number of different edge condition evaluations supported in a sequence of statements reflecting the ability to map such statements to supported primitive elements, particularly in FPGAs.

Upvotes: 4

Martin Thompson
Martin Thompson

Reputation: 16792

Can you declare a clocked process without a sensitivity list?

Yes:

process
begin
   wait until rising_edge(clk);
   q <= d;
end process;

or even simpler (although it doesn't look like a process, it effectively is one):

q <= d when rising_edge(clk);

Both forms are synthesisable with the tools I've tried (XST, Synplify, Quartus)

Upvotes: 1

Jan Decaluwe
Jan Decaluwe

Reputation: 2445

A process with a sensitivity list is a handy special case.

First, only a process without wait statements can have a sensitivity list. Second, such a process is equivalent to a process without sensitivity list and with an additional wait statement as the last statement. That wait statement specifies the equivalent sensitivity.

Therefore, in theory a process with a sensitivity list is optional. In practice however, the modeling case it covers is very common. Using a sensitivity list when possible is the better modeling option for clarity.

Upvotes: 1

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