CODEWITHSUNDEEP
vhdlintelfpgaintel-fpgaquartus
Daniil Smirnov
Daniil Smirnov

Reputation: 28

If sensitivity list in VHDL is not synthesizable, why does it gives an error due the Analysis and Synthesis?

To provide sequential logic in design with VHDL I have to use process statement, which has sensitivity_list. From different sources I know, that sensitivity list is non-synthesizable construction, i.e., if I will synthesize this code:

    ...
    process(c)
    b <= a and c;
    end process;
    ...

I would not have any latch by c signal, it will just be a usual AND-gate. But, when I synthesize code without sensitivity list:

    ...
    process
    b <= a and c;
    end process;
    ...

no matter what version of VHDL I choose, I get the same problem:

Error (10442): VHDL Process Statement error at process_test.vhd(79): Process Statement must contain either a sensitivity list or a Wait Statement

My question is: why does synthesizer care about sensitivity list? In my understanding, it is over-concerned about customers and this cannot be an error, but a critical warning, or even nothing, and warnings only when the simulation is on.

UPD. Here is full code and some images. I used Quartus Prime Standard 16.1

    library ieee;
    use ieee.std_logic_1164.all;
    entity stck_ovflw is
        port 
        (
            a       : in std_logic;
            c       : in std_logic;
            b       : out std_logic
        );
    end entity;
    architecture rtl of stck_ovflw  is
    begin
        process(c)
        begin
            b <= a AND c;
        end process;
    end rtl;

RTL Synthesis: enter image description here Modelling: enter image description here

Upvotes: 0

Views: 3492

Answers (2)

Giampietro Seu
Giampietro Seu

Reputation: 816

I think you are a little confused about the sensitivity_list. The sensitivity_list is a list of signals that trigger an activation of the process. Each time one of the signals in the sensitivity_list changes, the process is activated and the statements are evaluated.

In your example:

process(c) begin
    b <= a and c;
end process;

The process is activated only when c changes. This means that b takes a new value when c changes, but keeps the old value when a changes. This is not the behavior of a simple combinatorial AND gate and some sort of memory element will be needed for the synthesis to store the value of b.

In order to infer a simple AND gate, you must include all the input signals in the sensitivity_list. This can be done manually as:

process(a, c) begin
    b <= a and c;
end process;

Or in VHDL 2008 automatically with the keyword all:

process(all) begin
    b <= a and c;
end process;

Upvotes: 1

Matthew
Matthew

Reputation: 13947

It is the job of a logic synthesiser to generate a circuit that behaves exactly the same as your RTL. A process without a sensitivity list or a wait if an infinite loop and so cannot be simulated. Therefore, given my first sentence, how can a logic synthesiser possibly generate a circuit that behaves exactly the same as your RTL?

This should never be a problem, because you should always simulate before you synthesise. So, you should have fixed this before the logic synthesiser ever sees your code.

Upvotes: 1

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