CODEWITHSUNDEEP
verilogfpga
BruceV
BruceV

Reputation: 113

Entries in Verilog always sensitivity list

Can't find anything on this, it doesn't fit in well with keywords. Somewhere I came across a statement that it's bad practice to put some things in an always block sensitivity list. Things other than clk and other related internal signals within the device can, according to the statement, cause routing inefficiencies.

I find it convenient when coding relatively slow applications to generate subdivided clock signals, and use these in always blocks.

For Example:

reg Counter [12:0]    ;
reg SlowClk   ;

always @ (posedge clk)
    begin
    Counter <= Counter + 13'h1   ;
    SlowClk <= Counter[12]    ;
    end

always @ (posedge SlowClk)

Note: My text entry has one statement per line, if the lines are concatenated in the final post, that's due to the website.

Is there anything wrong with this?

Upvotes: 0

Views: 877

Answers (2)

Karan Shah
Karan Shah

Reputation: 1992

Yes this is indeed a bad practice. So you can do something different to get the SlowClk edge.

You can take a wire, to detect the SlowClk positive edge.

wire got_SlowClk_posedge;

Now to detect, SlowClk, positive edge, you need to have it's current and next clock values (Current Clock Value should be 0 & Next Clock Value should be 1) But fortunately, in your case, SlowClk, next clock value is the current value of Counter[12]. So you can use it.

assign got_SlowClk_posedge = Counter[12] & ~SlowClk;

So now your 2nd always block may look like this : 

// Instead of @(posedge SlowClk)
always @(posedge clk)
begin
  if(got_SlowClk_posedge)
  begin
    // Your code for positive edge of SlowClk
  end
end

Upvotes: 1

Dixita Patel
Dixita Patel

Reputation: 1

Nothing is wrong in this. If design required divided clock we must have to do this. but best practice is to use en signal for clock divider so that you can use same clock in every always block. And yes its good to use reset in clcok diveder (any sequential ckt required reset).

reg Counter [12:0]    ;
reg SlowClk   ;
reg div_clk ;
wire en;

always @ (posedge clk)
begin
if(!reset)
Counter <=  13'h0;
else
Counter <= Counter + 13'h1; 
end

assign  en  = (Counter ==13'h0)? 1'b1 : 1'b0;

always @ (posedge clk)
begin
if(!reset)
  div_clk = 1'b0;
else(en)
  div_clk <= ~div_clk;
end

Upvotes: 0

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