CODEWITHSUNDEEP
verilog
user2050932
user2050932

Reputation:

Verilog Multiple Signals Change In Sensitivity List of an Always Block

I was wondering whether it was possible for an always block to be executed only when multiple signals in the sensitivity list change together.

As in, suppose I have a signal 'in' and another 'posedge clk'. I want the always block to be executed when BOTH the signals change. Is it possible, and if yes, what is the syntax for it?

Upvotes: 3

Views: 8541

Answers (2)

Morgan
Morgan

Reputation: 20514

This an answer to the original question, not the problem revealed in the comments

As @Tim has mentioned there is no hardware construct which can do this. always @(posedge clk) create flip-flops which sample the data on the edge of a clk.

always @* blocks create combinatorial logic which is evaluated by the simulator when ever the right hand side of an assignment or a select signal changes.

If you had multiple 1 bit signals driven from D-type flip-flops you could XOR (^) the input (D) and output (Q) to create a, 1 clock cycle wide, signal indicating the value has changed. These change signals could be combined to create an enable signal. Which is used as a select or enable for a flip-flop.

always @(posedge clk or negedge rst_n) begin
  if (~rst_n) begin
    //reset condition
  end
  else if (enabled)
    //Enabled condition
  end
  // no final else, everything will holds its value
end

Or may be as the enable for a latch :

//synopsys async_set_reset "rst_n"
always @* begin
  if (~rst_n) begin
    // Reset 
  end
  else if (latch_open) begin
    //next datavalue
  end
end

Upvotes: 2

Tim
Tim

Reputation: 35933

In general, no there is no way to do it, as this doesn't actually map to any kind of standard logic cells that one would typically synthesize. However if you describe what your ultimate goal is, I'm sure someone can point you in the right direction while still using synthesizable logic. I'm having a hard time imagining what you could want such a block for.

Upvotes: 3

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