CODEWITHSUNDEEP
verilogfpgaxilinxhdlvivado
ItM
ItM

Reputation: 331

Adding signal to sensitivity list synthesizes to a buffer?

I'm writing a simple D-flip-flop in Verilog and looking at what it synthesizes to. Here's what I have:

module d_flip_flop(
    input d,
    input clr,
    input clk,
    input ce,
    output reg q
);

always @(posedge clk) begin: d_flip_flop
    if (clr) begin
        q <= 1'b0; 
    end else if (ce) begin
        q <= d;
    end
end

endmodule
And it synthesizes to: enter image description here

However, making this change to the code and adding CE to the sensitivity list:

module d_flip_flop(
    input d,
    input clr,
    input clk,
    input ce,
    output reg q
);

always @(posedge clk or posedge ce) begin: d_flip_flop
    if (clr) begin
        q <= 1'b0; 
    end else if (ce) begin
        q <= d;
    end
end

endmodule

It synthesizes to: enter image description here

What is going on? Why would adding CE to the sensitivity list make this synthesize to a buffer?

Thanks!

Upvotes: 1

Views: 570

Answers (1)

Justin N
Justin N

Reputation: 911

You're probably confusing the synthesis tool with that construct because it's not a normal thing to do. (There's nothing in the FPGA that directly supports that and I doubt it's even synthesizable at all.)

On the other hand, if you changed ce to clr in the sensitivity list, you should get a register with clr as an asynchronous reset, as that's the normal way to code that up for Xilinx.

I tried synthesizing it with Vivado and got a strange warning that didn't make sense. It's probably close enough to an async reset template that it doesn't directly error out, but ultimately not synthesizable so ends up with the output connected to GND.

Upvotes: 3

Related Questions