CODEWITHSUNDEEP
verilogsystem-veriloghdlsynopsys-vcs
TheSprintingEngineer
TheSprintingEngineer

Reputation: 319

Why always block not reactivating when there is a reassignment of logic described in sensitivity list

Signal driver_a is reassigned in the always block back to 0, but why is the always block not activating and assign value to driver_b ?

always @(driver_a) begin
driver_b = driver_a;
driver_a = 0;
end

initial begin
driver_a = 0; driver_b = 0;
#2 driver_a = 8'h8;
#2 driver_a = 8'hf;
end

In the waveform, I expect that after driver_a assigns its value to driver_b, then in the next line when driver_a gets assigned to 0, I'd expect the always block to reactivate and assign value 0 back to driver_b.

however this is not the case, the waveform seems to show that once the driver_a gets assigned to 0 in the always block, the always block does not reactivate and assign 0 back to driver_b's value. In short I'd expect driver_b's value to always remain 0, since code within an always block executes in zero simulation time.

I have attached the image of the resulting waveform, below

DVE Waveform of results

Upvotes: 1

Views: 315

Answers (1)

dave_59
dave_59

Reputation: 42698

Because the code is interpreted as single ordered set of statements. It's the same as if you had written 

always begin
     @(driver_a)           // 1
     driver_b = driver_a;  // 2
     driver_a = 0;         // 3
end

Statement //1 means "Wait for driver_a to change" Statement //2 means "Change driver_b to the value of driver_a" Statement //3 means "Change driver_a to 0"

Because the always block is a single thread that executes the statements in serial order, the change from //3 has already happened when it loops back to execute //1.

Upvotes: 1

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