Reputation: 53
When I run the following Verilog code I get an error:
warning: @* found no sensitivities so it will never trigger.
module main;
reg b;
always @(*) begin
$display("entered always block/n");
end
endmodule
Could someone please elaborate on this? Is there any way I can use $display
without "sensitivity list"?
Upvotes: 1
Views: 902
Reputation: 62037
Your simulator is correctly warning you of an unusual situation. That $display
statement will never be executed. Hence, it is useless code.
The implicit sensitivity list (@*
) means that it will only be entered if some signal (like b
) changes value, and it is used on the right-hand side (RHS) of some expression inside the always
. The problem is that you do not have any signal inside your block. Refer to IEEE Std 1800-2017, section 9.4.2.2 Implicit event_expression list.
If you add b
to your trivial example, the always
block will be triggered if there is any change on b
:
module main;
reg b;
always @(*) begin
$display("entered always block and b=%b", b);
end
initial begin
b=0;
#50 $finish;
end
always #5 b = ~b;
endmodule
Outputs:
entered always block and b=0
entered always block and b=1
entered always block and b=0
entered always block and b=1
entered always block and b=0
entered always block and b=1
entered always block and b=0
entered always block and b=1
entered always block and b=0
entered always block and b=1
Runnable example on edaplayground.
Upvotes: 2
Reputation: 42658
The always
construct introduces a procedural sequence of code that loops endlessly. It must have at least one procedural blocking construct, otherwise it gets into an infinite zero-delay loop. And that prevents anything else from executing.
The intended use of always
is to wait for some signal to change, or wait for some time delay. But if you only want the $display
to execute once, use initial
instead of always
and it will start executing the procedural sequence once at time 0, and not loop.
Upvotes: 0