CODEWITHSUNDEEP
verilogsystem-veriloghardware
user3212932
user3212932

Reputation: 17

harware implemenation of multiplier

i am trying to write a verilog code for harware implemenation of multiplier...but i am getting certain error my code is

here i take 4 bit input and 4 bit output....and then muliply first bit of multiplier with multiplicand...and store result in p...similarly second bit of multiplier with multiplicand and store in q...which further i took one 5 bit register and sote value in it....ansd so on for rest code

    module multiplier(a,b,c
        );

    input [3:0]a;
    input [3:0]b;
    output [7:0]c;

    wire [3:0]p;
    wire [3:0]q;
    wire [3:0]r;
    wire [3:0]s;
    wire [4:0]t;
     wire [5:0]u;
     wire [6:0]v;
     assign [3:0]p = {4{b[0]}} & [3:0]a ;   ////////ERROR///////
    assign [3:0]q = {4{b[1]}} & [3:0]a ;


    assign [3:0]r = {4{b[2]}} & [3:0]a ;
    assign [3:0]s = {4{b[3]}} & [3:0]a ;

    assign [4:1]t = [3:0]q;
    assign [5:2]u = [3:0]r;
    assign [6:3]v = [3:0]s;
    endmodule

    ERROR:HDLCompilers:26 - "multiplier.v" line 34 unexpected token: '['
    ERROR:HDLCompilers:26 - "multiplier.v" line 34 unexpected token: '['
    ERROR:HDLCompilers:26 - "multiplier.v" line 34 expecting ';', found ':'
    ERROR:HDLCompilers:26 - "multiplier.v" line 34 expecting 'endmodule', found '0'

Upvotes: 0

Views: 220

Answers (1)

Greg
Greg

Reputation: 19104

Brackets ([]) on the left of a signal name is only used with defining a packed array. After that the brackets are used to the right of the signals.

Example, your:

assign [3:0]p = {4{b[0]}} & [3:0]a ;

should be:

assign p[3:0] = {4{b[0]}} & a[3:0] ;

or use the full range:

assign p = {4{b[0]}} & a ;

Upvotes: 2

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