Verilog error for 2d array declaration

Question

• I wrote this code for register file in verilog.

• There is error in 2d array declaration of data that it is not declared.

• I am using ModelSim Altera 10.1d

  model RegFile(clk,reset,ReadReg1,ReadReg2,WriteData,WriteReg,RegWrite,ReadData1,ReadData2);
  
  input clk,reset,RegWrite;
  input [1:0] ReadReg1,ReadReg2,WriteReg;
  input [31:0] WriteData;
  output [31:0] ReadData1,ReadData2;
  reg [31:0] d,q1,q2,q3,q4,q;
  reg [3:0] decoutp;
  reg clkwrite,
  reg [31:0] data [3:0];
  reg [31:0] ReadData1,ReadData2;
  
  initial
  begin
  d = 32'h00000000;
  data[0] = 32'd101;
  data[1] = 32'd234;
  data[2] = 32'd260;
  data[3] = 32'd120;
  end
  
  always@(posedge clk)
  begin
  if(reset)
  begin
  reg32bit(q1,d,clk,reset);
  reg32bit(q2,d,clk,reset);
  reg32bit(q3,d,clk,reset);
  reg32bit(q4,d,clk,reset);
  end
  
  else
  begin
  //Write
  decoder2_4(decoutp,WriteReg);
  clockgate(clkwrite,RegWrite,clk,decoutp);
  reg32bit(q,WriteData,clkwrite,reset);
  
  //Read
  if(ReadReg1 == 2'b00) ReadData1 = data[0];
  else if(ReadReg1 == 2'b01) ReadData1 = data[1];
  else if(ReadReg1 == 2'b10) ReadData1 = data[2];
  else ReadData1 = data[3];
  
  if(ReadReg2 == 2'b00) ReadData2 = data[0];
  else if(ReadReg2 == 2'b01) ReadData2 = data[1];
  else if(ReadReg2 == 2'b10) ReadData2 = data[2];
  else ReadData2 = data[3];
  
  end
  end
  
  endmodule
  

• Error -

  (1)v(9): near "reg": syntax error, unexpected reg, expecting IDENTIFIER or
  TYPE_IDENTIFIER

  (2)v(15): (vlog-2730) Undefined variable: 'data'.

Answer 1

The given array syntax is supported in SystemVerilog .sv reg [31:0] data [3:0];

Answer 2

insert a semicolon after the clkwrite. like this

 reg clkwrite; 
reg [31:0] data [3:0];

and remove the instantiation of submodule inside the always block

Answer 3

Looks like you have a typo. There's a comma after the clkwrite declaration.