CODEWITHSUNDEEP
arrayscompiler-errorssyntax-errorverilogxilinx
Suguresh Kumar Arali
Suguresh Kumar Arali

Reputation: 47

Verilog error while declaring a array

reg [11:0] rom_sin_type [0:4095]= '{12'h000, 12'h003, 12'h006, 12'h009, 12'h00d, 12'h010, 12'h013, 12'h016, .....};

In verilog,when i am synthesizing the above line of code which contains 4096 values, each of 12 bit, its showing error as below given.

expecting ';', found '='

expecting 'endmodule', found '{'

Please can anyone help me , how to overcome this problem?

Upvotes: 0

Views: 659

Answers (2)

Greg
Greg

Reputation: 19122

Verilog does not support the '{} syntax. It is a SystemVerilog (IEEE Std 1800-2012) feature; refer to § 5.10 Structure literals, § 5.11 Array literals, § 7.2.2 Assigning to structures, § and 10.9 Assignment patterns.

You can either enable SystemVerilog (all modern Verilog simulators are SystemVerilog simulators) or assign the the Verilog way:

reg [11:0] rom_sin_type [0:4095];
initial begin
  rom_sin_type[0] = 12'h000;
  rom_sin_type[1] = 12'h003;
  rom_sin_type[2] = 12'h006;
  rom_sin_type[3] = 12'h009;
  .....
end

Upvotes: 3

Sourabh
Sourabh

Reputation: 674

You can try for loop also.

genvar  i;
for (i=0;i<4096;i= i+1) begin
    assign a[i] = i;
end

I am not sure whether the rom_sin_type will require an assign statement or not.

Upvotes: 0

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