CODEWITHSUNDEEP
arraysvhdl
jerp
jerp

Reputation: 257

VHDL unconstrained array of unconstrained array

I would like to have an 2D array in which both dimensions are sized based on entity generics, and I would like to pass these throughout my design into input/output ports of other components.

The easy solution has always been to create a package with constants defined that will create the correct sized types within the package...and use that package anywhere that the type is needed.

The problem is that when a user instantiates my pcore for Xilinx EDK, the user can configure things in the "Customize IP" interface and these options will get instantiated as generics into my design. There is no way the user can configure the IP and have the settings change the constants defined in a package.

Is there a way to do this purely from entity generics?

Upvotes: 2

Views: 1312

Answers (1)

Kevin Thibedeau
Kevin Thibedeau

Reputation: 3411

This is possible in VHDL-2008 either with package generics or directly with unconstrained arrays of unconstrained arrays. Unfortunately you will have to wait for synthesis vendor support to use it some time in the future. For now you will have to make do with flattening it into a 1D array and slicing out the segments you need to simulate two dimensions.

Upvotes: 0

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