CODEWITHSUNDEEP
vhdl
Tricky
Tricky

Reputation: 4461

How to constrain dimension in uncosntrained array when 1st is already constrained?

With VHDL 2008, you are allowed to define unconstrained types/subtypes. For example:

slv_array_t is array(natural range <>) of std_logic_vector;

then you can create subtypes where one or more dimensions is left open to be constrained later.

subtype slv32_array_t is slv_array_t(open)(31 downto 0);
signal some_object  : slv32_array_t(7 downto 0);

This is fine when the open dimensions are the first ones. But how can I constrain a subtype if the unconstrained dimension is not the first one? The following gives the error inn ActiveHDL that the dimension is already constrained.

Index constraint cannot be applied to constrained type.

subtype slv_array8_t is slv_array_t(7 downto 0)(open);  -- legal
signal some_object : slv_array8_t(31 downto 0);

The following also compains with the same error:

signal some_object : slv_array8_t(7 downto 0)(31 downto 0);

So, is there actually a way this type can be constrained in an object with VHDL 2008? Did it even make it into VHDL 2019?

Upvotes: 1

Views: 985

Answers (1)

Matthew
Matthew

Reputation: 13937

You just need to use (open) to "jump over" the constrained dimension, just like you did with the subtype:

signal some_object : slv_array8_t(open)(31 downto 0);

library IEEE;
use IEEE.std_logic_1164.all;

entity E is
end entity E;

architecture A of E is
  type slv_array_t is array(natural range <>) of std_logic_vector;
  subtype slv32_array_t is slv_array_t(open)(31 downto 0);
  signal some_object  : slv32_array_t(7 downto 0);
  subtype slv_array8_t is slv_array_t(7 downto 0)(open);  -- legal
  signal some_object2 : slv_array8_t(open)(31 downto 0);
begin
end architecture A;

https://www.edaplayground.com/x/reNU

Upvotes: 2

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