CODEWITHSUNDEEP
verilogxilinx
user3507563
user3507563

Reputation: 27

Signal EXCEPTION_ACCESS_VIOLATION received xilinx

I'm trying to make an arithmetic logic unit in verilog and I received the following error when I tried to simulate in ISim Simulator (No errors reported at Behavioral Check Syntax):

ERROR:Simulator:754 - Signal EXCEPTION_ACCESS_VIOLATION received

Here is the code:

module alu(
input [3:0] right,
input [3:0] left,
input [2:0] sel,
input CarryIn,
output reg CarryOut,
output reg [3:0] out
);


function [3:0] add;
input [3:0] a;
input [3:0] b;
input CarryIn;
assign add = a + b + CarryIn;
endfunction

function [3:0] substract;
input [3:0] a;
input [3:0] b;
input CarryIn;
assign subtract = a - b + (~CarryIn);
endfunction

function [3:0] AND;
input [3:0] a;
input [3:0] b;
assign AND = {1'b0 , a & b};
endfunction

function [3:0] OR;
input [3:0] a;
input [3:0] b;
assign OR = {1'b0 , a | b};
endfunction

function [3:0] XOR;
input [3:0] a;
input [3:0] b;
assign XOR = {1'b0 , a ^ b};
endfunction

function [3:0] increment;
input [3:0] a;
assign increment = a + 1;
endfunction

function [3:0] left_shift;
input [3:0] a;
assign left_shift = a << 1;
endfunction

function [3:0] right_shift;
input [3:0] a;
assign right_shift = a >> 1;
endfunction

always @ (left or right or sel) begin
case (sel) 
0 : {CarryOut , out} = add(left,right,CarryIn); 
1 : {CarryOut , out} = substract(left,right,CarryIn); 
2 : {CarryOut , out} = AND(left,right); 
3 : {CarryOut , out} = OR(left,right); 
4 : {CarryOut , out} = XOR(left,right) ;
5 : {CarryOut , out} = increment(left); 
6 :       begin
      CarryOut = left[3]; 
         out = left_shift(left);
         end
7 :       begin
      CarryOut = left[0]; 
         out = right_shift(left);
      end            
default : {CarryOut , out} = {1'b0,left};
endcase
                     end
endmodule

Any ideas ?

Upvotes: 0

Views: 6068

Answers (2)

Md Majumder
Md Majumder

Reputation: 31

One of the reasons for happening this is that the simulator does not understand a syntax. I had run into similar problem in VIVADO for a silly mistake while writing a verilog syntax. For a concatenation in verilog, mistakenly i used ":" instead of ",". That caused the same problem. To find out exactly which module is causing the problem it is good to look at the tcl console message. The module causing the problem is simply after compiling which module this message shows.

This is silly but sometimes it may take a lot of time to figure out.

Upvotes: 0

Greg
Greg

Reputation: 19104

Remove the keyword assign from all your functions. assign statements are for continuous assignments that should only be declared in a module; not a task, function, initial or always.

There is a typo too. A couple places you have "substract" and should be "subtract".

You are also missing CarryIn from your sensitivity list. If your sensitivity list is not complete it will infer complex latching logic. Better yet, switch to a IEEE 1364-2001 coding style and use always @(*) or always @* instead of always @ (left or right or sel or CarryIn). They auto construct the sensitivity list for combinational logic.

Upvotes: 1

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