CODEWITHSUNDEEP
makefile
Bertrand Caron
Bertrand Caron

Reputation: 2657

Make : Get dependencies of a target inside another one

I often find myself trying to reference the dependency of a target (Target1) inside another one (Target2).

Consider the following Makefile. How nice would be a $(deps target-name) function ! 

Rule1 : file1 file2 file3
    echo $^ # Careful, these are whitespaces, not a tab !

Rule2 : file4 file5 file6
    echo $^ # Careful, these are whitespaces, not a tab !

clean-Rule-1-2 : 
    rm $(deps Rule1) $(deps Rule2)   # Careful, these are whitespaces, not a tab !

I found this link mentioning that one could build himself his own dependency list, but it's looks rather tedious.

Does any one have a better solution (assuming none are natively implemented in the Makefile) and/or workflow tips referring to this issue ?

Upvotes: 2

Views: 410

Answers (1)

MadScientist
MadScientist

Reputation: 100836

Why do you want to list prerequisites of a clean-type rule? That just forces make to build those dependencies if they're out of date, only to delete them again.

There is no way to do what you want because it is not possible to be consistent about it. For example, your rules could be written like this:

Rule1 : file1 file2 file3
        echo $^ # Careful, these are whitespaces, not a tab !

clean-Rule-1-2 : $(deps Rule1)
        rm $^   # Careful, these are whitespaces, not a tab !

Rule1 : file10 file11 file12

Oops! When $(deps ...) is expanded make doesn't know about the extra three prerequisites and so they won't be listed. And that's not even considering implicit rules, where make doesn't know what the full prerequisite list is when it parses the makefile; it only computes them when it's trying to build the target.

You don't give a real example of what you want to do, but generally the way makefiles are written is that you put the prerequisites into variables, then you can use the variables in multiple places.

Upvotes: 2

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