CODEWITHSUNDEEP
verilog
user3761169
user3761169

Reputation: 11

How to return packed array to localparam in Verilog

I have a Verilog localparam and a function declared as: 

localparam [7:0] someParam[0:15] = someFunc(8'h10);

function [7:0][15:0] someFunc();
  input [7:0] some_input;

  someFunc[0]  = 8'h00;
  ...
  ...
endfunction

The error I get is: cannot assign packed to unpacked. Any solutions?

Thanks.

Upvotes: 0

Views: 4057

Answers (1)

Greg
Greg

Reputation: 19104

Verilog doesn't support multi-dimensional parameter arrays as stated in:

  • IEEE1364-1995 § 3.10 Parameters
  • IEEE1364-2001 § 3.11.1 Module parameters
  • IEEE1364-2005 § 4.10.1 Module parameters

There is a ways to do it with SystemVerilog. Multi-dimensional declarations are not supported, however a parameter type can be typdef which can be multi-dimensional. The same is true for the return type of a function. See IEEE1800-2012 § 6.20.1 Parameter declaration syntax and § 6.18 User-defined types.

Example:

typedef logic [7:0] someType [16];
localparam someType someParam = someFunc(8'h10);

function someType someFunc (input [7:0] some_input);
  someFunc[0]  = 8'h00;
  // ...
endfunction

Similarly, Verilog does not support double packed arrays (ex [7:0][15:0] someFunc).

  • IEEE1364-1995 § 10.3.1 Defining a function
  • IEEE1364-2001 § 10.3.1 Function declarations
  • IEEE1364-2005 § 10.4.1 Function declarations

SystemVerilog does support double packed arrays. So another solution is:

localparam [15:0][7:0] someParam = someFunc(8'h10);

function [15:0][7:0] someFunc (input [7:0] some_input);
  someFunc[0]  = 8'h00;
  // ...
endfunction

Note: you want [15:0][7:0] which is 16 arrays of 8-bits, not [7:0][15:0] which is 8 arrays of 16-bits.

Upvotes: 1

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