CODEWITHSUNDEEP
verilog
optimus
optimus

Reputation: 19

Passing arrays to verilog modules

I have a 2D array to pass to module.I have flattened it in 1D array and want to send it to some module for processing.For doing that I declared a 32 bit wide wire and tried passing the values of the 32 bit registers to other modules through it.It gave me an error "Procedural assignment to a non-register is not permitted." I wanted to know if there's any other way of doing this? And how can I rectify the error?

@Marty Thanks again.It's working.I have to calculate the mean for 1000 sampled floating point values.I have separate 4 modules for floating point addition arithmetic.I want to send each of these values one by one to the module.For that I am using a for loop.I am able to send it for 

Float_Add dummyinstance(fpvalue[k]);

Where k is some constant.

But not for

for(..)
  for(..)
     Mean[i]=Float_Add dummyinstance(fpvalue[i][j])

How can I do that?

Upvotes: 1

Views: 5095

Answers (1)

Marty
Marty

Reputation: 6654

Sounds like you're trying to assign to a wire within an always or initial block. Use assign if you want to change the value on a wire. If you'd prefer to use a procedural block (initial or always), you'll need to change the type of the port to a reg. ie:

module processor (
    input wire [31:0] flattened_bus_i,
    output wire [31:0] flattened_bus_w,
    output reg  [31:0] flattened_bus_r
);

    initial begin 
       flattened_bus_r = flattened_bus_i + 32'd1; 
    end

    assign flattened_bus_w = flattened_bus_i + 32'd1;

endmodule

In SystemVerilog, you should be able to have 2D arrays as ports.

Upvotes: 2

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