How to right shift a bit in Verilog?

Question

I have a code like the one below:

module scheduler(clk, rst, busy, s);

input clk, rst;
input [3:0] busy;

output [3:0] s;

reg [3:0] s;

wire busyor;
assign busyor = busy[0] | busy[1] | busy[2] | busy[3];

always  @ (posedge clk or negedge rst)
  if       (!rst)     s  <=  4'b1000;
  else if  (!busyor)  s  <=  s >>> 1;

endmodule

The point is that "s" starts as 1000, and then it shifts all the way until 0001, and then when it shifts again, it becomes 0000. The point is that when the bit reaches the end, meaning when it is 0001, and when it is shifted again, I want it to appear at the beginning, meaning it to rotate. So, after 0001 if shift comes, it should go to 1000. Any way to achieve it?

Answer 1

Yes, there is a way to achieve that. For example:

s <= {s[0],s[3:1]}