Reputation: 972
I am trying to build a test bench in SystemVerilog using a clocking block cb_module
.
I am running Modelsim from the command line:
vsim -c test_bench -do "run -all"
Everything works fine but I can not figure out how to get Modelsim to exit and return with a non-zero exit code if assertions like these fails:
##1 assert(cb_module.dat_o == 4'h0) else $finish;
Upvotes: 4
Views: 10099
Reputation: 11
If you must call $finish for some reason (e.g. it's called from within your test framework, and you can't modify it), you can get your exit code out to the caller using "onfinish stop". Example:
vsim -c test_bench -do "onfinish stop; run -all"
(I used Modelsim 10.3d; I'm not sure if this is available in older versions.)
Upvotes: 1
Reputation: 42698
You don't want to use $finish
to exit the simulator - that is considered a normal exit.
You should use $error or $fatal:
##1 assert(cb_module.dat_o == 4'h0) else $fatal("dat_o not 0");
Then you can script that into your -do file. After the run
command returns, the script should call runStatus
or runStatus -full
to determine if the run terminated for normal or abnormal reasons. Once the script determines that the script terminated because a user error, it can then call quit -code <n>
and return any non-zero number to indicate the failure condition.
Many tests do not want to exit the simulator on an assertion failure, so they use $error. You can then use the command
coverage attribute -name TESTSTATUS
and it will return a severity code for the most severe message generated during your test run. So you may ultimately want to do
quit -code [coverage attribute -name TESTSTATUS -concise]
Upvotes: 12
Reputation: 7573
I don't think you really have any control over that. I think the exit code has more to do with whether the program executed successfully or encountered and internal error. This is probably why most regression tools parse the log files and grep for error messages to figure out if a run failed.
Upvotes: 0