CODEWITHSUNDEEP
verilogmodelsim
Abhishek Tyagi
Abhishek Tyagi

Reputation: 153

Verilog simulation error in Modelsim 10.4 SE

CODE://Gate level description of a 2x4_decoder

module decoder_2X4_gates(D,A,B);
output [0:3] D;
input  A,B;
wire A_not, B_not;
not f1(A_not,A);
not f2(B_not,B);
nand f4(D[0],A_not,B_not);
nand f5(D[1],A_not,B);
nand f6(D[2],A,B_not);
nand f7(D[3],A,B);
endmodule;

ERROR: can't read "Startup(-L)": no such element in array

Load canceled

Upvotes: 1

Views: 8174

Answers (2)

Gonzalo Larralde
Gonzalo Larralde

Reputation: 3541

In my case I was receiving the very same error. After digging I figured out that the license file wasn't installed. After installing the License file I was able to move forward as expected.

Upvotes: 0

Morgan
Morgan

Reputation: 20544

Not sure on the issue with forcing values from the waveform window, but I would suggest creating a testbench, whereby you can just execute the simulation and see results.

ie:

module tb;

  reg A;       //Test Input
  reg B;       //Test Input
  wire [3:0] D;//Test Output

  //Device Under Test
  decoder_2X4_gates dut (
    .A (A),
    .B (B),
    .D (D)
  );

  //Test Program
  initial begin
    A=1'b0;
    B=1'b0;
    #1ps $displayb(D);

    #1ns;
    A=1'b1;
    B=1'b0;
    #1ps $displayb(D);

    #1ns;
    A=1'b0;
    B=1'b1;
    #1ps $displayb(D);


    #1ns;
    A=1'b1;
    B=1'b1;
    #1ps $displayb(D);

    $finish;
  end

endmodule

There is a working example of this on EDA Playground.

Upvotes: 1

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