CODEWITHSUNDEEP
loopsfor-loopconcatenationsystem-verilog
user3714538
user3714538

Reputation: 13

Concatenation operator in System verilog in a loop

I am trying to do the following : concat = {concat[7:0],clk} inside a forever loop as below :

   bit [7:0]    concat;
   concat = 0;
   forever begin
        @(posedge clk);
        concat = {concat[7:0],clk};
    end

I wanted to know what value will it contain after 8 clock iterations at any point of time, if the initial value of concat = 0.

Can it be different from 'hAA or 'h55 at any point of time?

Upvotes: 1

Views: 2628

Answers (2)

dave_59
dave_59

Reputation: 42673

Since you have @(posdege clk), clk will always be 1 (or x) when evaluating the RHS of the assignment. So concat will be 'h00, 'h01, 'h03, 'h07, 'h17, ...

Also note that if any other thread tries to read concat on the same positive edge of clk, you have a race condition, so please use a NBA to make the assignment.

Upvotes: 0

Morgan
Morgan

Reputation: 20514

You can not just write concat = 0; you should either assign concat = 0; or 

initial begin
  concat = 0;
end

Forever can not be used like that, the only two top levels you're allowed are initial and always. You want some thing like the following for a simulation:

initial begin
  forever begin
    @(posedge clk);
    concat = {concat[6:0],clk};
  end
end

If you are writing for synthesis then you might want to imply a flip-flop:

always @(posedge clk) begin
  concat = {concat[6:0],clk};
end

Once you have fixed your RTL it should be easy to try out on EDA Playground.

Upvotes: 1

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