CODEWITHSUNDEEP
concatenationverilog
user1467945
user1467945

Reputation: 41

direction of verilog concatenation

I am a beginner in verilog.

Almost of all examples for concatenation are as the following.

wire [3:0] result;
reg  a, b, c, d;

result = {a, b, c, d};

Is the following possible, too?

wire [3:0] result;
wire a, b, c, d;

{a, b, c, d} = result;

Upvotes: 4

Views: 4218

Answers (1)

user597225
user597225

Reputation:

The LHS(left hand side) of assignments do allow concatenations.

module mod1;

wire [3:0] result;
wire a, b, c, d;

reg e,f,g,h;

{a, b, c, d} = result; //Invalid, not in procedural construct

assign {a, b, c, d} = result; //Valid
assign {a,{b,c},d}  = result; //Valid

initial 
   {e, f, g, h} = result; //Valid

endmodule

Upvotes: 6

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