CODEWITHSUNDEEP
hardwarechisel
Vikas Chauhan
Vikas Chauhan

Reputation: 31

For loop is not unrolling in chisel

I was trying to understand how we are generating verilog code out of "for" loop in chisel. Generally verilog code used to unroll body as many time as loop progress but here in chisel it's only unrolling it once.

val io = new Bundle {

    val a = UInt(INPUT, 2)

    val output = UInt(OUTPUT, 2)
  }

    io.output := UInt(0)

    for(j <- 0 to 4){

      io.output := io.a
    }

Corresponding verilog code for the above program is : 

module LutSimpleALU(

    input [1:0] io_a,
    output[1:0] io_output
);

   assign io_output = io_a;

endmodule

it would be very helpful if someone can tell how for loop is working.

Upvotes: 2

Views: 1732

Answers (1)

Chris
Chris

Reputation: 3987

Your for loop is doing the same thing for each iteration. You aren't using the "j" iterator variable anywhere, so this is what it expands to:

io.output := io.a
io.output := io.a
io.output := io.a 
io.output := io.a

The semantics here is that the last writer wins, so the last statement of "io.output = io.a" would be the final value. In fact, the previous three statements mean nothing, so they would be pruned from the graph.

Upvotes: 4

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