CODEWITHSUNDEEP
simulationverilog
Awais Hussain
Awais Hussain

Reputation: 442

Simulation in verilog using $monitor

I've been trying to implement full adder in Verilog. I have implemented it and it is also showing results on Isim. Only problem is that when I try to see the simulation using $monitor command, it is showing me only 1 result, not all simulation results. Here is testbench code:

module Full_adder_s2_testbench;

// Inputs
reg a;
reg b;
reg cin;

// Outputs
wire sum;
wire cout;

// Instantiate the Unit Under Test (UUT)
Full_adder_s2 uut (
    .a(a), 
    .b(b), 
    .cin(cin), 
    .sum(sum), 
    .cout(cout)
);
integer i;

initial begin
    // Initialize Inputs
    a = 0;
    b = 0;
    cin = 0;

    // Wait 100 ns for global reset to finish
    #100;

    end
    always @ ( a, b, cin )
            begin

            // generate truth table
            for ( i = 0; i < 8; i = i + 1 )
                    // every 10 ns set a, b, and cin to the binary rep. of i
                    #10 {a, b, cin} = i;
                    $monitor( "%d ns: a + b + cin = %b + %b + %b = cout sum = %b %b",
                                             $time, a, b, cin, cout, sum );  
            // stop 10ns after last change of inputs
            #10 $stop;
            end


endmodule

And here is result in ISIM:

# run 1000 ns 
Simulator is doing circuit initialization process.

Finished circuit initialization process.

                 400 ns: a + b + cin = 1 + 1 + 1 = cout sum = 1 1

Stopped at time : 410 ns :  in File "E:/Namal/FYP/My work/XILINX/Full_adder_s2/Full_adder_s2_testbench.v" Line 66

Upvotes: 0

Views: 3747

Answers (1)

Morgan
Morgan

Reputation: 20514

$monitor is only meant to be setup once and will trigger every time a signal changes, try using $display since you already have the statement inside of your always @*.

While learning Verilog I would encourage you to use begin end liberally. The issue is that only 1 line was in the for loop, the $display/$monitor was outside and so only executed once at the start.

always @* begin
  // generate truth table
  for ( i = 0; i < 8; i = i + 1 ) begin //<-- Added begin
    // every 10 ns set a, b, and cin to the binary rep. of i
    #10 {a, b, cin} = i;
    $display( "%d ns: a + b + cin = %b + %b + %b = cout sum = %b %b", $time, a, b, cin, cout, sum ); 
  end //<--Added end
  // stop 10ns after last input
  #10 $stop;

end

Full example on EDA Playground.

NB: it is best not to use manual sensitivity lists any more replace always @ ( a, b, cin ) with always @*. This will result in quicker refactoring and lowering the chance of RTL to gates simulation mismatch.

Upvotes: 4

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