CODEWITHSUNDEEP
windowsverilog
darkpunk
darkpunk

Reputation: 17

vcd not generating with right format

Why doesn't this Verilog code generate a VCD output file?

module t_Prob_5_48 (); 
reg x_in, clk, reset_b; 
wire y_out; 
Prob_5_48 M0 (y_out, x_in, clk, reset_b); 
initial #400 $finish; 
initial begin clk = 0; forever #5 clk = !clk; end
initial fork
reset_b = 0; 
#30 reset_b = 1; 
#30 x_in = 0; 
#100 reset_b = 0; 
#110 reset_b = 1; 
#110 x_in = 1; 
#200 reset_b = 0; 
#210 reset_b = 1; 
#210 x_in = 0; 
#220 x_in = 1; 
#300 reset_b = 0; 
#310 reset_b = 1; 
#310 x_in = 1; 
#330 x_in = 0;  
join
endmodule

Upvotes: 1

Views: 614

Answers (1)

toolic
toolic

Reputation: 62236

To generate a VCD file, you need to call $dumpvars in your Verilog file. For example:

initial $dumpvars;

Refer to the IEEE Std 1800-2012, section 21.7 "Value change dump (VCD) files".

Upvotes: 1

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