CODEWITHSUNDEEP
vhdl
learner4
learner4

Reputation: 74

VCD dump (VHDL simulation with vcs )

I need help in simulating VHDL code with VCS. What are options available to dump vcd file with vcs for vhdl code .I have tried all the options, which i found on internet. None seems to be working, or i am not doing it in a correct way . A detailed answer would be helpful Commands tried till now:

    vcs test_top -R +vcs+vcdpluson -debug_pp
    vcs test_top -R +vcs+vcdpluson -debug_pp -vcd test.vcd
    vcs test_top -R +vcs+vcdpluson+vcd_file test.vcd -debug_pp
    vcs test_top -V -R +vcs+vcdpluson -debug_pp

Upvotes: 2

Views: 3231

Answers (0)

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