CODEWITHSUNDEEP
vhdl
Muhammed Ashraf
Muhammed Ashraf

Reputation: 3

Xillinx VHDL code error

I am trying to write a vhdl code am it gives me more am trying to write a code for a sequential with 5 states ( S0 , S1 , S2 , S3 , S4)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Seqq is
PORT ( seq , clk , reset : IN std_logic;
       output : OUT std_logic;
         leds : OUT std_logic_vector( 2 downto 0) );
end Seqq;


architecture Behavioral of Seqq is
type states IS ( S0 , S1 , S2 , S3 , S4);
signal nxt , prst : states ;
begin
FB:PROCESS(reset, clk)
begin
if Rising_edge(clk) then
 if reset = '1' then prst <='0';

else prst <= nxt ;
end if ;
end if ;
end process FB;comb:PROCESS( prst) 
begin 
case prst IS 
when S0 =>
If seq = '0' then nxt <= S0;
elsif seq = '1' then nxt <= S1;
end if ;
leds <= "000";
output <= '0';

when S1 =>
If seq = '0' then nxt <= S2;
elsif seq = '1' then nxt <= S1;
end if ;
leds <= "001";
output <= '0';

when S2 =>
If seq = '0' then nxt <= S2;
elsif seq = '1' then nxt <= S1;
end if ;
leds <= "010";
output <= '0';

when S3 =>
If seq = '0' then nxt <= S0;
elsif seq = '1' then nxt <= S4;
end if ;
leds <= "011";
output <= '0';

when S4 =>
If seq = '0' then nxt <= S0;
output <= '1';
elsif seq = '1' then nxt <= S1;
end if ;
leds <= "100";
output <= '0';
end case ;
end process comb;


end Behavioral;

and the error which I get is

Type of prst is incompatible with type of '0'.

what can I do?

Upvotes: 0

Views: 81

Answers (1)

MatthiasB
MatthiasB

Reputation: 1759

In this line 

if reset = '1' then prst <='0';

you are assigning a '0' to prst. If you look at your error message prst is incompatible with type of '0', you will see that the types don't match.

Investigating your type of prst, you will see that it is of type states, an enum ranging from S0 to S4. '0' however is of type std_logic or bit, which is not convertible to state.

So, what you propably want (if it is still ok with your logic) is to change assignment of prst to S0 instead:

if reset = '1' then prst <= S0;

Upvotes: 2

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