CODEWITHSUNDEEP
vhdl
zach thomas
zach thomas

Reputation: 1

Can someone help me find where I get stuck in a loop VHDL

I'm using a finite state machine for a project, but when I go to simulate it I get an iteration error when I send shift_button to be '1'. 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity LFSR_FSM is
    Port ( load_button : in  STD_LOGIC;
           input : in  STD_LOGIC_VECTOR (7 downto 0);
           key : inout  STD_LOGIC_VECTOR (7 downto 0);
           shift_button : in  STD_LOGIC;
              Clock : in STD_LOGIC);
end LFSR_FSM;
architecture Behavioral of LFSR_FSM is

type State_type is (Prime,Shift,Memory); 
signal Sreg, Snext: State_type; 
signal mem,shifted_output : STD_LOGIC_VECTOR (7 downto 0);
signal seven,six,five,four,three,two,one,zero : STD_LOGIC; 
begin
    process (Sreg,input,load_button,shift_button)
        begin 
        case Sreg is 
            when Memory => if shift_button = '1' then Snext <= Shift;
                               elsif load_button =  '1' then Snext <= Prime;
                                else Snext <= Memory; 
                           end if;  

            when Shift  => Snext <= Memory;


            when Prime => if load_button = '1' then Snext <= Prime;
                             else Snext <= Memory; 
                            end if;

            when others => Snext <= Memory; 
        end case;
end process; 
process (Clock)
    begin 
     if Clock'event and Clock = '1' then 
     Sreg <= Snext; 
     end if;
end process; 

--key <= output ;
with Sreg select 
key <= input when Prime,
       shifted_output when Shift,
         mem when others;
mem <= key;
shifted_output<=(zero,seven,six,five,four,three,two,one);
    seven <= mem(7); 
    six <= mem(6); 
    five <=  mem(0) xor mem(6);
    four <= mem(0) xor mem(5);
    three <= mem(0) xor mem(4);
    two <= mem(2);
    one <= mem(1);
    zero <= mem(0); 
end Behavioral;

This is what I have at the end of my simulation load_button<= '1' after 20 ns, '0' after 30 ns,'1' after 40 ns, '0' after 50 ns;
input<= "00110100" after 10 ns; shift_button<= '1' after 60 ns, '0' after 70 ns;

Upvotes: 0

Views: 223

Answers (1)

Kevin Thibedeau
Kevin Thibedeau

Reputation: 3411

You have a combinational loop involving key -> mem -> (numbers) -> shifted_output -> key when the FSM enters the Shift state. That is causing your simulator to iterate through delta cycles until it hits its limit. I suggest registering the key signal by moving the with-select into the clocked process. It can remain unchanged if using VHDL-2008 or translated to a case statement with earlier standards.

Upvotes: 2

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