CODEWITHSUNDEEP
integervhdl
July
July

Reputation: 442

unsigned to integer conversion VHDL

I'm trying to convert an unsigned(7 downto 0) data to an integer!

I have this

SIGNAL SQ_X1: INTEGER RANGE 0 TO 1024:= conv_integer(pos_ini_x);

where pos_ini_x comes from another module that is the result of a random number calculation. Syntax issues are good but when I convert to assign to SQ_X1 variable, it doesn't work well, it always provide a zero as a result.

If you know how to improve this conversion and resolve this problem and explain why it happens, could you help me please?

It would be appreciated.

Upvotes: 0

Views: 941

Answers (1)

Kevin Thibedeau
Kevin Thibedeau

Reputation: 3411

You are applying conv_integer as an initializer to the signal. It is only called once during elaboration when pos_ini_x is presumably 0. If you want to update the SQ_X1 signal after elaboration you have to use a signal assignment to change it.

Note that conv_integer is a nonstandard function. The standard equivalent in ieee.numeric_std is to_integer.

Upvotes: 3

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