Reputation: 514
Here is my simple code segment
class sample_sequence extends uvm_sequence#(sample_sequence_item);
rand int no_txn;
`uvm_object_param_utils_begin(sample_sequence_item)
`uvm_field_int(no_txn,UVM_ALL_ON)
`uvm_object_utils_end
rand sample_sequence_item sample_sequence_item_inst;
function new(string name="sample_sequence");
super.new(name);
endfunction
virtual task body();
no_txn = 10;
for(int i = 0;i<no_trn;i++) begin
sample_sequence_item_inst = sample_sequence_item::type_id::create($sformatf("sample_sequence_item_%0d",i));
sample_sequence_item_inst.addr = $urandom_range(0,20);
start_item(sample_sequence_item_inst);
finish_item(sample_sequence_item_inst);
end
endtask: body
endclass
The sequence just generates random addresses and sends to driver. I want to control the parameter no_txn from the test.
I can do that using the hierarchy for the sequence but is there any UVM based factory method to override it?
Upvotes: 0
Views: 2935
Reputation: 7573
I depends on how you start the sequence.
If you start it in the test directly, you can just add a constraint when randomizing the sequence:
class some_test extends uvm_test;
// ...
task run_phase(uvm_phase phase);
sample_sequence seq = sample_seq::type_id::create("seq");
if (!seq.randomize() with { no_txn == 5; })
`uvm_fatal("RANDERR", "Randomization error")
seq.start(sequencer);
endtask
endclass
If you are extending a test where you started it similarly to what I showed above (minus the with
block), then you can create a child class where you add a specific constraint:
class some_other_sequence extends some_sequence;
constraint do_5_items { no_txn == 5; }
endclass
Somewhere else in your test you'll have to set a type override (I usually do it in the end_of_elaboration_phase(...)
function). You can read more about type overrides and the factory in the UVM user guide.
Upvotes: 1