CODEWITHSUNDEEP
uvm
nguthrie
nguthrie

Reputation: 2685

Get response from sequence to control virtual sequence

I need to verify a function which will take an unknown number of cycles to complete. I can determine that it is done by reading some registers and comparing their values to a model.

I have a sequence extended from uvm_reg_sequence which does this checking. I need this sequence to run at the end of my virtual sequence, and if the check fails, loop back to the beginning of the virtual sequence to run some more cycles. I will repeat this until the check passes (or I hit some timeout).

What I think I need is a way for the virtual sequence to get a response from the checker sequence to control this loop. What is the recommended way for accomplishing this?

Upvotes: 0

Views: 810

Answers (1)

Tudor Timi
Tudor Timi

Reputation: 7573

The simplest thing I can think of is a simple check_passed field inside your register sequence":

class some_reg_sequence extends uvm_reg_sequence;
  bit check_passed;

  task body();
    some_reg.read();
    if (<pass_condition>)
      check_passed = 1;
  endtask
endclass

The virtual sequence would just check this field after executing the register sequence:

class virtual_sequence extends uvm_sequence;
  task body();
    some_reg_sequence reg_sequence;
    `uvm_create_on(reg_sequence, ...)

    // do stuff
    // ...

    do
      reg_sequence.start();
    while (!reg_sequence.check_passed);
  endtask
endclass

You can also implement a timeout by wrapping the do..while inside a fork...join_any, together with a wait statement.

Upvotes: 2

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